Reconstruction of signal timing in integrated circuits
Improved integrated circuits, memory devices, circuitry, and data methods are described that facilitate the adjustment and reconstruction of signal timing of devices by providing for an interface having inputs and/or outputs that are adjustably delayed. This allows embodiments of the present invention to sense the signal delay and utilize adjustable input or output delays to correct the signal timing relationships such that correctly timed communication signals are received by the internal circuitry of the device. In one embodiment of the present invention, a register is utilized to adjust the timing delay of individual input and/or output signals for the device. This increases the robustness of the device and its resistance to communication or data corruption, allowing larger ranges of environmental conditions and input capacitances of systems or communication busses to be tolerated.
1. A method of operating an integrated circuit device, comprising:
receiving a first plurality of signals on a plurality of signal lines;
determining a relative timing of the first plurality of signals; and
determining desired delays for a first subset of signal lines of the plurality of signal lines in response to the relative timing of the first plurality of signals.
2. The method of claim 1 , further comprising:
adjusting delays of the first subset of signal lines in response to the desired delays for the first subset of signal lines.
3. The method of claim 2 , wherein adjusting the delays further comprises selecting a number of delay elements for coupling to the first subset of signal lines in response to the desired delays and selectively coupling the selected number of delay elements to the first subset of signal lines.
4. The method of claim 3 , further comprising receiving a second plurality of signals on the plurality of signal lines after coupling the selected number of delay elements to the first subset of signal lines.
5. The method of claim 4 , further comprising:
receiving a third plurality of signals on the plurality of signal lines;
determining a relative timing of the third plurality of signals;
determining desired delays for a second subset of signal lines of the plurality of signal lines in response to the relative timing of the third plurality of signals;
adjusting delays of the second subset of signal lines in response to the desired delays for the second subset of signal lines; and
restoring signal lines of the first subset of signal lines to an undelayed state if not contained in the second subset of signal lines.
6. The method of claim 3 , wherein selecting the number of delay elements comprises selecting a number of delay elements for each signal line of the first subset of signal lines that is dependent upon the desired delay for that signal line.
7. The method of claim 6 , wherein selecting a number of delay elements for each signal line of the first subset of signal lines comprises selecting zero or more delay elements for each of the signal lines.
8. The method of claim 1 , wherein determining the desired delays comprises determining the delays necessary to bring each of the first plurality of signals to a desired relative timing.
9. The method of claim 1 , wherein the first subset of signal lines is a null set.
10. The method of claim 1 , wherein determining the relative timing of the first plurality of signals comprises starting a counter in response to receiving a first signal and determining a count for each remaining signal in response to receiving each remaining signal.