DRAM-based CAM cell with shared bitlines
View Patent ↗A CAM cell is disclosed that includes a comparator and two three-transistor (3T) DRAM cells connected to a pair of associated bit lines. Data is stored using intrinsic capacitance of each 3T DRAM cell, and is applied to the gate terminal of a pull-down transistor of the comparator. During refresh operations, inverted data values are written onto the bit lines, and subsequently written from the bit lines to the 3T DRAM cells. In ternary embodiments, an inverting refresh circuit is used to re-invert the inverted data values prior to being written to the 3T DRAM cells. In one embodiment, the 3T DRAM cells are cross-coupled to the bit lines, and the inverting refresh circuit transfers bits from one bit line to the other.
1. A content addressable memory (CAM) cell comprising:
a first DRAM data cell including a first read port, a first write port, and a first storage node for storing a first data value;
a second DRAM data cell including a second read port, a second write port, and a second storage node for storing a second data value; and
a comparator coupled to the first and second storage nodes,
wherein the first read port is coupled to one of the first write port and the second write port.
2. The CAM cell in claim 1 , wherein the first read port is coupled to the first write port.
3. The CAM cell in claim 2 , wherein the second read port is coupled to the second write port.
4. The CAM cell in claim 1 , wherein the first read port is coupled to the second write port.
5. The apparatus of claim 4 , wherein the second read port is coupled to the first write port.
6. A content addressable memory (CAM) array comprising:
a first DRAM data cell including a first read port, a first write port, and a first storage node for storing a first data value;
a second DRAM data cell including a second read port, a second write port, and a second storage node for storing a second data value;
a comparator coupled to the first and second storage nodes;
a first bit line coupled to the first read port and one of the first write port and the second write port;
a second bit line coupled to the second read port and one of the second write port and the first write port; and
a refresh circuit connected to the first and second bit lines.
7. The CAM array of claim 6 , wherein the first bit line is coupled to the first read port and the first write port.
8. The CAM array of claim 7 , wherein the second bit line is coupled to the second read port and the second write port.
9. The CAM array of claim 6 , wherein the first bit line is coupled to the first read port and the second write port.
10. The CAM array of claim 9 , wherein the second bit line is coupled to the second read port and the first write port.
11. A content addressable memory (CAM) cell array comprising a plurality of CAM cells, each CAM cell including a first dynamic random access memory (DRAM) cell for storing a first bit of a data value, and a comparator circuit for discharging a match line when an applied data value fails to match the stored data value, wherein the first DRAM cell comprises:
a first transistor connected between a storage node and a first bit line, the first transistor having a gate terminal controlled by a write word line;
a second transistor having a gate terminal connected to the storage node, and a first terminal connected to ground; and
a third transistor connected between a second terminal of the second transistor and the first bit line,
wherein the storage node is connected to a first input terminal of the comparator circuit.
12. The CAM cell array according to claim 11 , wherein the comparator circuit comprises a fourth transistor connected in series with a fifth transistor between the match line and a discharge line,
wherein a gate terminal of the fourth transistor is connected to the first input terminal, and
wherein a gate terminal of the fifth transistor comprises a second input terminal of the comparator circuit for receiving a first bit of the applied data value.
13. The CAM cell array according to claim 11 , further comprising a refresh circuit including a first portion connected to the first bit line, the first portion comprising:
a first transmission gate connected between the first bit line and a first node;
a first inverter connected between the first node and a second node; and
a second transmission gate connected between the second node and the first bit line.
14. A content addressable memory (CAM) cell array comprising:
a plurality of CAM cells including a first CAM cell including a first three-transistor dynamic random access memory (3T DRAM) cell for storing a first data bit of a two-bit data value, the first 3T DRAM cell being connected to a first bit line, a second 3T DRAM cell for storing a second data bit of the two-bit data value, the second 3T DRAM cell being connected to a second bit line, and a comparator connected to the first and second 3T DRAM cells for discharging a match line when an applied complementary data value fails to match a complementary two-bit data value stored by the first and second 3T DRAM cells; and
means for controlling the first and second 3T DRAM cells to write inverted first and second data bits onto the first and second bit lines, respectively, during a first operating period, for inverting the inverted first and second data bits, and for writing the re-inverted first and second data bits to the first and second bit lines, respectively, during a second operating period, and for writing the re-inverted first and second data bits from the first and second bit lines, respectively, onto the first and second 3T DRAM cells, respectively, during a third operating period.
15. A content addressable memory (CAM) cell array comprising a plurality of CAM cells, each CAM cell being connected to first and second associated bit lines and including a first dynamic random access memory (DRAM) cell for storing a first data bit of a two-bit data value, a second DRAM cell for storing a second data bit of the two-bit data value, and a comparator circuit for discharging a match line to a discharge line when an applied data value fails to match the two-bit data value stored by the first and second DRAM cells,
wherein the first DRAM cell includes:
a first transistor connected between a storage node and the first bit line, the first transistor having a gate terminal controlled by an associated write word line;
a second transistor having a gate terminal connected to the storage node, and a first terminal connected to ground; and
a third transistor connected between a second terminal of the second transistor and the second bit line,
wherein the storage node is connected to a first input terminal of the comparator circuit.
16. The CAM cell array according to claim 15 , wherein the comparator circuit comprises a fourth transistor connected in series with a fifth transistor between the match line and the discharge line,
wherein a gate terminal of the fourth transistor is connected to the first input terminal, and
wherein a gate terminal of the fifth transistor comprises a second input terminal of the comparator circuit for receiving a first bit of the applied data value.
17. The CAM cell array according to claim 15 , further comprising a refresh circuit including a first portion comprising:
a first transmission gate connected between the second bit line and a first node;
a first inverter connected between the first node and a second node; and
a second transmission gate connected between the second node and the first bit line.
18. A content addressable memory (CAM) cell array comprising:
a plurality of CAM cells including a first CAM cell connected to a first bit line and a second bit line, the first CAM cell including a first three-transistor dynamic random access memory (3T DRAM) cell for storing a first data bit of a two-bit data value, a second 3T DRAM for storing a second data bit of the two-bit data value, and a comparator connected to the first and second 3T DRAM cells for discharging a match line when an applied data value fails to match the two-bit data value stored by the first and second 3T DRAM cells; and
means for controlling the first and second 3T DRAM cells to write data bits onto the second and first bit lines, respectively, during a first operating period, and for controlling the first and second 3T DRAM cells to subsequently write data bits from the first and second bit lines to the first and second 3T DRAM cells, respectively, thereby refreshing the data values stored in said first and second 3T DRAM cells.
19. A memory array comprising:
a first three-transistor dynamic random access memory (3T DRAM) cell for storing a first data bit, the first 3T DRAM cell having a first write transistor connected to a first bit line and a first read transistor connected to a second bit line; and
a second 3T DRAM for storing a second data bit, the second 3T DRAM cell having a second write transistor connected to the second bit line and a second read transistor connected to the first bit line.
20. The memory array according to claim 19 , further comprising a write word line connected to a gate terminal of the first write transistor and to a gate terminal of the second write transistor.
21. The memory array according to claim 19 , further comprising a read word line connected to a gate terminal of the first read transistor and to a gate terminal of the second read transistor.
22. The memory array according to claim 19 , further comprising a refresh circuit including:
a first transmission gate connected between the second bit line and a first node;
a first inverter connected between the first node and a second node;
a second transmission gate connected between the second node and the first bit line;
a third transmission gate connected between the first bit line and a third node;
a second inverter connected between the third node and a fourth node; and
a fourth transmission gate connected between the fourth node and the second bit line.
23. The memory array according to claim 19 , further comprising:
means for temporarily storing first and second data from the first and second bit lines, respectively; and
means for generating and driving the compliments of the first and second stored data onto the second and first bit lines, respectively.
24. The memory array according to claim 19 , wherein the first and second 3T DRAM cells form a content addressable memory (CAM) cell further comprising a comparator having a first terminal connected to a storage node of the first 3T DRAM cell and a second terminal connected to a storage node of the second 3T DRAM cell.