Method for fabricating semiconductor device
View Patent ↗A method for fabricating a semiconductor device capable of preventing an electric short between lower electrodes caused by leaning lower electrodes, or lifted lower electrodes and of securing a sufficient capacitance of a capacitor by increasing an effective capacitor area. The method includes the steps of: preparing a semi-finished semiconductor substrate; forming a sacrificial layer on the semi-finished semiconductor substrate; patterning the sacrificial layer by using an island-type photoresist pattern, thereby obtaining at least one contact hole to expose portions of the semi-finished semiconductor substrate; and forming a conductive layer on the sacrificial layer.
1. A method for fabricating a semiconductor device, comprising the steps of:
forming a plurality of plugs electrically connected to a substrate by passing through an inter-layer insulation layer;
forming an etch stop layer on the inter-layer insulation layer and the plugs;
forming a sacrificial layer on the substrate;
patterning the sacrificial layer by using an island-type photoresist pattern, thereby obtaining at least one contact hole to expose portions of the inter-layer insulation layer; and
forming a conductive layer on the sacrificial layer.
2. The method of claim 1 , wherein the step of obtaining said at least one contact hole includes the steps of:
forming the island-type photoresist pattern on the sacrificial layer;
etching the sacrificial layer with use of the photoresist pattern as an etch mask to expose predetermined portions of the etch stop layer;
removing the exposed portions of the etch stop layer to expose the portions of the inter-layer insulation layer; and
removing the photoresist pattern.
3. The method of claim 2 , after the step of forming the conductive layer, further including the steps of:
planarizing the conductive layer until the sacrificial layer is exposed;
removing the patterned sacrificial layer; and
forming lower electrodes by removing the conductive layer disposed on the inter-layer insulation layer.
4. The method of claim 2 , wherein at the step of forming the island-type photoresist pattern, the photoresist pattern is formed such that the photoresist pattern masks regions of the sacrificial layer where the lower electrodes are formed and opens the rest regions of the sacrificial layer.
5. The method of claim 4 , wherein the lower electrodes is made of a material selected from a group consisting of Pt, Rh, Ru, Ir, Os, Pd, PtO x , RhO x , RuO x , IrO x , OsO x , PdO x , CaRuO 3 , SrRuO 3 , BaRuO 3 , BaSrRuO 3 , CaIrO 3 , SrIrO 3 , BaIrO 3 , (La,Sr)CoO 3 , Cu, Al, Ta, Mo, W, Au, Ag, WSi x , TiSi x , MOSi x , CoSi x , NoSi x , TaSi x , TiN, TaN, WN, TiSiN, TiAlN, TiBN, ZrSiN, ZrAlN, MoSiN, MoAlN, TaSiN, and TaAlN and the combination thereof.
6. The method of claim 3 , wherein the lower electrodes are formed in a cylinder structure.
7. The method of claim 1 , wherein the etch stop layer is used as a part of the lower electrode.
8. The method of claim 7 , wherein the etch stop layer is made of a material selected from a group consisting of polysilicon, Ti, TiN, WSi x and Al.
9. The method of claim 7 , wherein the etch stop layer is made of a material selected in combination from a group consisting of polysilicon, Ti, TiN, WSi x and Al.
10. The method of claim 1 , wherein at the step of etching the sacrificial layer, the predetermined portions of the etch stop layer corresponds to regions except for regions where the lower electrodes are formed.
11. The method of claim 1 , further including the step of forming a layer for use in a hard mask after the step of forming the sacrificial layer and the step of etching the layer for use in the hard mask by using the island-type photoresist pattern as an etch mask after the step of forming the island-type photoresist pattern.
12. The method of claim 1 , wherein the sacrificial layer is made of an oxide-based material.
13. A method for fabricating a semiconductor device, comprising the steps of:
forming a plurality of plugs electrically connected to a substrate by passing through an inter-layer insulation layer;
forming a conductive etch stop layer on the inter-layer insulation layer and the plugs;
forming a sacrificial insulation layer on the etch stop layer;
forming an island-type photoresist pattern on the layer;
etching the sacrificial insulation layer with use of the photoresist pattern as an etch mask to expose predetermined portions of the etch stop layer;
removing the exposed portions of the etch stop layer to expose portions of the inter-layer insulation layer;
removing the photoresist pattern;
forming a conductive layer on the sacrificial insulation layer and a remaining portion of the etch stop layer;
planarizing the conductive layer until the sacrificial insulation layer is exposed;
removing the sacrificial insulation layer; and
forming lower electrodes by removing the conductive layer disposed on the inter-layer insulation layer.