Content addressable memory (CAM) cell bit line architecture
View Patent ↗A ternary content addressable memory (TCAM) cell ( 100 ) can include two memory elements ( 102 - 0 and 102 - 1 ) with a single bit line ( 106 - 0 and 106 - 1 ) per memory element. A TCAM cell ( 100 ) can also include a compare stack ( 104 ) and two word lines ( 114 and 116 ) that can connect to each memory element ( 102 - 0 and 102 - 1 ). The memory elements ( 102 - 0 and 102 - 1 ) can include SRAM type memory cells with one of two data terminals connected to a pre-write potential (Vpre, which can be a ground potential, or the like). Write operations can include pre-setting the data values of memory elements ( 102 - 0 and 102 - 1 ) to the pre-write potential prior to providing write data via the bit lines ( 106 - 0 and 106 - 1 ).
1. A content addressable memory (CAM) cell, comprising:
at least two memory elements configured to provide first and second data values to a compare stack that provides a compare indication between a compare data value and the first and second data values, the compare stack comprises at least one discharge path coupled between a match line and a predetermined voltage node that is allowed to float in a compare operation, each memory element comprising
a first controllable impedance path coupled to a first bit line that is controlled in response to a first word line, and
a second controllable impedance path coupled to a predetermined logic level that is controlled in response to a second word line different from the first word line.
2. The CAM cell of claim 1 , further comprising:
the compare stack comprises parallel discharge paths between the match line and the predetermined voltage node, at least one of the discharge paths being enabled in a first compare result, and both discharge paths being disabled in a second compare result.
3. The CAM cell of claim 1 , wherein:
the compare stack comprises a first discharge path having two transistors coupled in series, one discharge path receiving a compare data value and the first data value, the other discharge path receiving a complementary compare data value and the second data value.
4. The CAM cell of claim 1 , wherein:
the compare stack provides the compare indication in a compare operation; and
the predetermined voltage node is a pseudo-supply voltage node placed to a set voltage in a pre-compare operation preceding the application of compare data values and allowed to float in the compare operation that compares the compare data value to the stored data values.
5. The CAM cell of claim 4 , wherein:
the set voltage is selected from the group consisting of a low power supply voltage and ground.
6. The CAM cell of claim 4 , wherein:
the predetermined logic level is also the pseudo-supply voltage level, and the pseudo-supply voltage level is a pseudo-ground voltage that is discharged in a pre-write operation that precedes the application of write data from the bit lines to the respective memory elements.
7. The CAM cell of claim 4 , further including:
a sense amplifier that senses a differential voltage between input terminals, the sense amplifier having one input terminal coupled to the match line and another input terminal coupled to the pseudo-supply voltage.
8. The CAM cell of claim 1 , wherein:
the predetermined logic level is selected from the group consisting of a lower power supply voltage and ground.
9. The CAM cell of claim 1 , wherein:
the compare stack provides the compare indication in a compare operation; and
the predetermined logic level is a pseudo-supply voltage placed to a set voltage in a pre-compare operation preceding the application of compare data values and allowed to float in a compare operation that compares the compare data value to the stored data values.
10. The CAM cell of claim 1 , wherein:
the compare stack provides an exclusive OR type function between the compare data value and the first and second data values.
11. The CAM cell of claim 1 , wherein:
each memory element comprises a static random access memory storage structure.
12. The CAM cell of 1 , wherein:
each memory element comprises a dynamic random access memory storage structure.
13. A content addressable memory cell comprising:
at least one static random access memory (SRAM) type storage element for storing a data value, the storage element comprising
no more than one bit line;
a pre-write transistor having a current path coupled to a power supply terminal and a control terminal coupled to a first word line, the power supply terminal being allowed to float during a compare operation between the data stored in the storage element and a compare data value; and
an access transistor having a current path coupled to the one bit line and a control terminal coupled to a second word like different from the first word line.
14. The storage element of claim 13 , wherein:
the power supply terminal is coupled to an essentially constant power supply voltage selected from the group consisting of a low power supply voltage and ground.
15. The storage element of claim 13 , wherein:
the power supply terminal is coupled to a pseudo-supply voltage placed to one voltage prior to the application of write data on the one bit line, and allowed to float during the compare operation.
16. The storage element of claim 15 , wherein:
the cone voltage is a low power supply voltage.
17. The storage element of claim 13 ; further including:
an exclusive-OR type comparator having one input coupled between the pre-write transistor and the access transistor and at least one other input coupled to receive a compare data value.