Content addressable and random access memory devices having high-speed sense amplifiers therein with low power consumption requirements
View Patent ↗Content addressable memory (CAM) devices include at least one CAM array that is configured to identify at least one match between a new search word and entries therein by performing a staged compare operation that conserves bit line power by initially floating at least some of a plurality of bit lines in said CAM array and then driving the at least some of a plurality of bit lines with second bits of the new search word in response to detecting at least one partial match between first bits of the new search word and the entries in said CAM array.
1. A sense amplifier, comprising:
an unbalanced pair of cross-coupled transistors;
a first precharge signal line electrically coupled to a first current carrying terminal of a first transistor in said unbalanced pair;
a second precharge signal line electrically coupled to a first current carrying terminal of a second transistor in said unbalanced pair; and
an enable transistor having a first current carrying terminal electrically connected to second current carrying terminals of the first and second transistors and a second current carrying terminal electrically coupled to a reference signal line.
2. The sense amplifier of claim 1 , wherein the first precharge signal line is a match line of a CAM array; and wherein the reference signal line is a pseudo-ground line of the CAM array.
3. The sense amplifier of claim 1 , wherein the second transistor has a lower threshold voltage than the first transistor.
4. The sense amplifier of claim 1 , wherein the second transistor is wider than the first transistor.
5. A content addressable memory (CAM) device, comprising:
at least one CAM array block that is configured to perform a staged search operation across a plurality of segmented rows of CAM cells in said CAM array block using a plurality of pseudo-ground line signals to assess which first ones of a plurality of precharged final segment match line signals represent match conditions and which second ones of a plurality of precharged final segment match line signals represent miss conditions.
6. A sense amplifier, comprising:
an unbalanced pair of NMOS transistors;
a first precharge signal line electrically coupled to a first current carrying teminal of a first NMOS transistor in said unbalanced pair and a gate terminal of a second NMOS transistor in said unbalanced pair;
a second precharge signal line electrically coupled to a first current carrying terminal of the first NMOS transistor and a gate terminal of the second NMOS transistor; and
an enable transistor having a first current carrying terminal electrically connected to second current carrying terminals of the first and second NMOS transistors and a second current carrying terminal electrically coupled to a reference signal line that is switched high-to-low to enable a sense operation in the sense amplifier.
7. The sense amplifier of claim 6 , wherein the second NMOS transistor is wider than the first NMOS transistor.
8. The sense amplifier of claim 6 , wherein the second NMOS transistor has a lower threshold voltage than the first NMOS transistor.
9. The sense amplifier of claim 8 , wherein the second NMOS transistor is wider than the first NMOS transistor.
10. The sense amplifier of claim 9 , wherein the first precharge signal line is a match line of a CAM array; and wherein the second precharge signal line is a pseudo-ground line of the CAM array.
11. The sense amplifier of claim 10 , wherein the match line is electrically coupled to the gate terminal of the second NMOS transistor by a PMOS resistor.
12. The sense amplifier of claim 6 , wherein the first precharge signal line is a match line of a CAM array.
13. The sense amplifier of claim 12 , wherein the second precharge signal line is a pseudo-ground line of the CAM array.
14. The sense amplifier of claim 12 , wherein the match line is electrically coupled to the gate terminal of the second NMOS transistor by a PMOS resistor.
15. The sense amplifier of claim 6 , further comprising a PMOS pull-up transistor having a drain terminal electrically coupled to the first current carrying terminal of the second NMOS transistor.
16. The sense amplifier of claim 15 , wherein a gate terminal of said enable transistor is responsive to a clock signal; and wherein a gate terminal of said PMOS pull-up transistor is responsive to another clock signal.
17. The sense amplifier of claim 15 , wherein the first precharge signal line is a match line of a CAM array; wherein the second precharge signal line is a pseudo-ground line of the CAM array; and wherein the match line is electrically coupled to the gate terminal of the second NMOS transistor by a PMOS resistor.
18. The sense amplifier of claim 6 , wherein a gate terminal of said enable transistor is responsive to a clock signal.