Semiconductor formation method that utilizes multiple etch stop layers
View Patent ↗The present invention is a semiconductor contact formation system and method. Contact insulation regions are formed with multiple etch stop sublayers that facilitate formation of contacts. This contact formation process provides relatively small substrate connections while addressing critical lithographic printing limitation concerns in forming contact holes with small dimensions. In one embodiment, a multiple etch stop insulation layer comprising multiple etch stop layers is deposited. A contact region is formed in the multiple etch stop insulation layer by selectively removing (e.g., etching) some of the multiple etch stop insulation layer. In one embodiment, a larger portion of the multiple etch stop insulation layer is removed close to the metal layer and a smaller portion is removed closer to the substrate. The different contact region widths are achieved by performing multiple etching processes controlled by the multiple etch stop layers in the multiple etch stop insulation layer and spacer formation to shrink contact size at a bottom portion. Electrical conducting material (e.g., tungsten) is deposited in the contact region.
1. A contact formation process comprising;
preparing a silicon wafer substrate;
forming a gate region;
creating source and drain regions;
depositing a multiple etch stop insulation layer, wherein depositing said multiple etch stop insulation layer comprises:
depositing a first etch stop layer directly on said silicon wafer substrate in a contact region;
depositing a first sub interlevel dielectric layer over said first etch stop layer;
depositing a second etch stop layer over said first sub interlevel dielectric layer, wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer; and
depositing a second sub interlevel dielectric layer over said second etch stop layer;
forming said contact region in said multiple etch stop insulation layer by selectively removing some of said multiple etch stop insulation layer and forming a sub spacer region such that a substrate coupling area of said contact region is smaller than a metal layer coupling area of said contact region; and
depositing electrical conducting material in said contact region.
2. A contact formation process of claim 1 wherein said first etch stop layer is in a range of about 300 to 800 Šthick, said first sub interlevel dielectric layer is in a range of about 1,000 to 2,000 Šthick, said second etch stop layer is in a range of about 300 to 800 Šthick and said second sub interlevel dielectric layer is in a range of about 10 Kű1 KŠthick.
3. A contact formation process of claim 1 wherein said forming said contact region in said multiple etch stop insulation layer comprises:
etching away a portion of said second sub interlevel dielectric layer;
removing a portion of said second etch stop layer;
depositing spacer dielectric material and etching to form said sub spacer region;
etching away a portion of said first sub interlevel dielectric layer; and
removing a portion of said first etch stop layer.
4. A contact formation process of claim 3 wherein an area of said portion of said first sub interlevel dielectric layer etched away is smaller than an area of said portion of said second sub interlevel dielectric layer that is etched away due to sub spacer formation.
5. A contact formation process of claim 4 wherein said area of said portion of said first sub interlevel dielectric layer etched away is a range of about 0.06 μm to 0.13 μm wide and said area of said portion of said second sub interlevel dielectric layer that is etched away is in the range of about 16 μm to 0.18 μm wide.
6. A contact formation process of claim 1 further comprising depositing an anti reflective coating layer.
7. A contact formation process of claim 1 wherein said forming said gate region comprises:
depositing a gate insulation layer;
depositing a control gate layer; and
removing said gate insulation layer and said control gate layer from non gate region areas.
8. A contact formation process of claim 6 further comprising forming a floating gate.
9. A contact formation process comprising:
depositing a multiple etch stop insulation layer comprising a first etch stop layer and a second etch stop layer wherein said first etch stop layer and said second etch stop layers have similar selectivity characteristics, said first etch stop layer formed in an area directly next to a substrate corresponding to a contact region and under a first sub interlevel dielectric layer and said second etch stop layer formed under a second interlevel dielectric layer, wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer, wherein said multiple etch stop insulation layer is formed utilizing a lithography process;
creating said contact region in said multiple etch stop insulation layer, wherein said creating of said contact region includes forming sub-spacer regions in removed portions of said second sub interlevel dielectric layer and said second etch stop layer, wherein a non-lithography spacer formation process is also utilized to achieve a contact bottom; and
depositing a conducting material in said contact region.
10. A contact formation process of claim 9 wherein depositing said multiple etch stop insulation layer comprises:
depositing said first etch stop layer;
depositing said first sub interlevel dielectric layer;
depositing said second etch stop layer, and
depositing said second sub interlevel dielectric layer.
11. A contact formation process of claim 9 comprising:
etching away a portion of said second sub interlevel dielectric layer;
removing a portion of said second etch stop layer;
depositing spacer dielectric material and etching to form said sub-spacer regions;
etching away a portion of said first sub interlevel dielectric layer; and
removing a portion of said first etch stop layer.
12. A contact formation process of claim 11 wherein said first etch stop layer and second etch stop layer are nitride.
13. A contact formation process of claim 11 wherein said sub spacer regions comprise nitride or SiON.
14. A contact formation process of claim 9 wherein said contact bottom dimension has a range of about 0.06 μm to 0.13 μm.
15. A contact formation process comprising:
depositing a first etch stop layer directly on a substrate in a contact region;
depositing a first sub interlevel dielectric layer over said first etch stop layer;
depositing a second etch stop layer over said first sub interlevel dielectric layer, wherein said second etch stop layer has similar selectivity characteristics as said first etch stop layer and wherein said first sub interlevel dielectric layer is between said first etch stop layer and said second etch stop layer;
depositing a second sub interlevel dielectric layer over said second etch stop layer;
creating said contact region in said first etch stop layer, said first sub interlevel dielectric layer, second etch stop layer, and said second sub interlevel dielectric layer, wherein said creating of said contact region comprises:
etching away a portion of said second sub interlevel dielectric layer;
removing a portion of said second etch stop layer;
depositing spacer dielectric material;
etching said spacer dielectric material to form a first sub-spacer region and a second sub-spacer region, wherein said first and second sub spacer regions define an exposed portion of said first sub interlevel dielectric layer that is in the range of about 0.06 μm to 0.13 μm wide;
etching away said exposed portion of said first sub interlevel dielectric layer; and
removing a portion of said first etch stop layer; and
depositing a conducting material in said contact region, wherein said conducting material forms a contact bottom that is in the range of about 0.06 μm to 0.13 μm wide.