IP Library Granted Patent US 7,192,869
Granted Patent B2
US 7,192,869 · App. 10/935,662 · Granted Mar 20, 2007

Methods for planarizing a metal layer

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Quick Facts
Patent No.
US 7,192,869
App. No.
10/935,662
Granted
Mar 20, 2007
Kind
B2
Abstract

Methods for planarizing a metal layer in a semiconductor device are disclosed. An illustrated example method comprises dividing a metal layer into a first section and a second section. A polishing removal rate associated with the first section is greater than a polishing removal rate associated with the second section. The method also includes forming an oxide layer on the first section of the metal layer; and planarizing the oxide layer and the metal layer using a chemical mechanical polishing process.

Claims (30)

1. A method for planarizing a metal layer comprising:

forming the metal layer on a wafer having a first section and a second section, wherein a polishing removal rate associated with the first section is greater than a polishing removal rate associated with the second section;

forming a first oxide layer on the first section of the metal layer, wherein a surface of the second section remains substantially free of oxide or has a second oxide layer thereon that is thinner than the first oxide layer; and

chemical mechanical polishing the first oxide layer and the metal layer to remove the first oxide layer and planarize the metal layer.

2. A method as defined in claim 1 , wherein the first section comprises a center area of the wafer.

3. A method as defined in claim 1 , wherein the metal layer comprises a copper layer.

4. A method as defined in claim 1 , wherein the first section comprises an outer edge of the wafer.

5. A method as defined in claim 4 , wherein the metal layer comprises a copper layer.

6. A method as defined in claim 1 , further comprising a third section between to first and second sections.

7. A method as defined in claim 6 , further comprising forming a third layer onto third section.

8. A method as defined in claim 7 , wherein the first oxide layer is thicker than the third oxide layer.

9. A method as defined in claim 8 , wherein the metal layer comprises a copper layer.

10. A method as defined in claim 6 , further comprising forming the second oxide layer on the second section.

11. A method as defined in claim 10 , wherein the second oxide layer is thicker than any third oxide layer in the third section.

12. A method as defined in claim 11 , wherein the metal layer comprises a copper layer.

13. A method as defined in claim 6 , wherein the first, second and third sections are concentric.

14. A method as defined in claim 1 further comprising:

forming an interlayer dielectric layer on a wafer; and

forming the metal layer by depositing conductive material on the interlayer dielectric layer.

15. A method as defined in claim 14 further comprising forming a via hole in the interlayer dielectric layer.

16. A method as defined in claim 14 , wherein the chemical mechanical polishing process results in the metal layer being coplanar with the interlayer dielectric layer.

17. A method for planarizing a metal layer comprising:

forming an oxide layer on a first section of a metal layer without forming an oxide layer on a second a section of the metal layer, wherein a polishing removal rate associated with the first section is greater than a polishing removal rate associated with the second section; and

removing the oxide layer and planarizing the metal layer using a chemical mechanical polishing process.

18. A method for planarizing a metal layer comprising:

forming a first oxide layer on a first section of a metal layer;

forming a second oxide layer on a second section of the metal layer, wherein the first oxide layer is thicker than the second oxide layer, and a polishing removal rate associated with the first section is greater than a polishing removal rate associated with the second section; and

removing to first and second oxide layers and planarizing the metal layer using a chemical mechanical polishing process.

19. A method as defined in claim 18 , wherein the first oxide layer has a thickness of 1200˜1600 Å.

20. A method as defined in claim 18 , wherein the second oxide layer has a thickness of 200˜600 Å.

Assignments (11)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 23, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041363/0441 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 22, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041347/0694 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR PREVIOUSLY RECORDED ON REEL 017749 FRAME 0335. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNOR SHOULD BE "DONGBUANAM SEMICONDUCTOR INC.". Recorded Jun 21, 2006
From: DONGBUANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017821/0670 →
CHANGE OF NAME Recorded Jun 8, 2006
From: DONGANAM SEMICONDUCTOR INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017749/0335 →
MERGER Recorded Mar 2, 2006
From: ANAM SEMICONDUCTOR INC.
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 017243/0464 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 7, 2004
From: LEE, JOO HYUN
To: ANAM SEMICONDUCTOR INC.
Reel/Frame 015780/0253 →