Programmable delay circuit within a content addressable memory
View Patent ↗An apparatus having an output register coupled to a content addressable memory (CAM) array. The output register may be configured to output data based on a delayed clock signal. A programmable delay circuit may be coupled to receive a reference clock signal and generate the delayed clock signal using one or more delay elements.
1. An apparatus, comprising:
a content addressable memory (CAM) array;
an output register coupled to the CAM array, the output register configured to output data based on a delayed clock signal;
a programmable delay circuit coupled to receive a reference clock signal and generate the delayed clock signal using a delay element;
a second programmable delay circuit coupled between the programmable delay circuit and the output register;
wherein the reference clock signal is received at a clock pad and wherein the programmable delay circuit is coupled between the clock pad and the output register; and
wherein the programmable delay circuit and the second programmable delay circuit each comprises a separate programmable register.
2. The apparatus of claim 1 , wherein the programmable delay circuit comprises:
a plurality of the delay elements to generate a plurality of delayed clock signals;
a programmable register to store information indicating a particular delayed clock signal of the plurality of delayed clock signals; and
a multiplexer coupled with the programmable register and the plurality of delay elements to select the particular delayed clock signal based on the information.
3. The apparatus of claim 2 , wherein the programmable delay circuit further comprises a decoder coupled to the programmable register to decode the information stored in the programmable register.
4. The apparatus of claim 2 , wherein each of the plurality of delay elements provides a different time period of delay to the reference clock signal.
5. The apparatus of claim 4 , wherein one of the plurality of delay elements provides substantially a zero time period of delay.
6. The apparatus of claim 4 , wherein at least one of the plurality of delay elements comprises a series of inverters.
7. The apparatus of claim 1 , further comprising an instruction decoder coupled to the clock pad to receive the reference clock signal.
8. The apparatus of claim 2 , wherein the information for the programmable register indicates the particular delayed clock signal according to a frequency of the reference clock signal.
9. The apparatus of claim 1 , wherein the programmable delay circuit is a first programmable delay circuit comprising:
a first plurality of the delay elements to generate a first plurality of delayed clock signals;
a first programmable register to store first information indicating a first particular delayed clock signal of the first plurality of delayed clock signals; and
a first multiplexer coupled with the first programmable register and the first plurality of delay elements to select the first particular delayed clock signal based on the first information.
10. The apparatus of claim 9 , wherein the second programmable delay circuit comprises:
a second plurality of the delay elements to receive the first particular delayed clock signal and generate a second plurality of delayed clock signals, and wherein the second programmable register is to store second information indicating a second particular delayed clock signal of the second plurality of delayed clock signals; and
a second multiplexer coupled with the second programmable register and the second plurality of delay elements to select the second particular delayed clock signal based on the second information.
11. The apparatus of claim 1 , further comprising a processor coupled to the clock pad to transmit the reference clock signal.
12. The apparatus of claim 1 , further comprising a processor coupled with the output register to receive the data.
13. The apparatus of claim 1 , further comprising a read circuit coupled between the CAM array and the output register.
14. The apparatus of claim 1 , wherein the CAM array comprises a plurality of rows of CAM cells each having a corresponding match line.
15. The apparatus of claim 14 , further comprising a match flag circuit coupled to the match lines and the output register.
16. The apparatus of claim 14 , further comprising an encoder circuit coupled to the match lines and the output register.
17. An apparatus, comprising:
a content addressable memory (CAM) array;
an output register coupled to the CAM array, the output register configured to output data based on a delayed clock signal;
a first programmable delay circuit coupled to receive a reference clock signal and generate the delayed clock signal using a delay element; and
a second programmable delay circuit coupled with the first programmable delay circuit;
wherein the first programmable delay circuit includes:
a first plurality of the delay elements to generate a first plurality of delayed clock signals,
a first programmable register to store first information indicating a first particular delayed clock signal of the first plurality of delayed clock signals, and
a first multiplexer coupled with the first programmable register and the first plurality of delay elements to select the fist particular delay clock signal based on the first information; and
wherein the second programmable delay circuit includes:
a second plurality of the delay elements to receive the first particular delayed clock signal and generate a second plurality of delayed clock signals,
a second programmable register to stored second information indicating a second particular delayed clock signal of the second plurality of delayed clock signals, and
a second multiplexer coupled with the second programmable register and the second plurality of delay elements to select the second particular delayed clock signal based on the second information.
18. An apparatus, comprising:
a content addressable memory (CAM) array;
an output register coupled to the CAM array, the output register configured to output data based on a delayed clock signal;
a first programmable delay circuit coupled to receive a reference clock signal and generate the delayed clock signal using a delay element; and
a second programmable delay circuit coupled with the first programmable delay circuit;
wherein the first programmable delay circuit includes:
a first plurality of the delay elements to generate a first plurality of delayed clock signals,
a first programmable register to store first information indicating a first particular delayed clock signal of the first plurality of delayed clock signals, and
a first multiplexer coupled with the first programmable register and the first plurality of delay elements to select the fist particular delay clock signal based on the first information; and
wherein the second programmable delay circuit includes:
a second plurality of the delay elements to receive the first particular delayed clock signal and generate a second plurality of delayed clock signals, the first programmable register for storing second information indicating a second particular delayed clock signal of the second plurality of delayed clock signals; and
a second multiplexer coupled with the first programmable register and the second plurality of delay elements to select the second particular delayed clock signal based on the second information.