IP Library Granted Patent US 7,348,268
Granted Patent B2
US 7,348,268 · App. 10/939,237 · Granted Mar 25, 2008

Controlled breakdown phase change memory device

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Quick Facts
Patent No.
US 7,348,268
App. No.
10/939,237
Granted
Mar 25, 2008
Kind
B2
Abstract

A phase change memory material may be deposited over an electrode in a pore through an insulator. The adherence of the memory material to the insulator may be improved by using a glue layer. At the same time, a breakdown layer may be formed in the pore between the memory material and electrode.

Claims (34)

1. A method comprising:

using a conductive layer to adhere a phase change material to an insulator; and

forming a dielectric layer between the phase change material and an electrode such that current between the phase change material and the electrode must pass through said dielectric layer.

2. The method of claim 1 including forming the insulator over said electrode and forming a pore in said insulator down to said electrode.

3. The method of claim 2 including forming said conductive layer over said insulator and forming said pore through said conductive layer and said insulator.

4. The method of claim 3 including forming said dielectric layer in said pore over said conductive layer.

5. The method of claim 4 including removing the portion of said dielectric layer over said conductive layer.

6. The method of claim 5 including using selective etching to remove said conductive layer.

7. The method of claim 5 including using a lift-off technique to remove said conductive layer.

8. The method of claim 1 including forming an upper electrode over said phase change material and forming a breakdown channel through said dielectric layer.

9. The method of claim 1 including selectively depositing said dielectric layer on said electrode.

10. The method of claim 1 including forming said dielectric layer over said electrode, depositing an etch stop layer over said dielectric layer, forming the insulator over said etch stop layer, and forming said conductive layer over said insulating layer.

11. The method of claim 10 including forming said pore through said conductive layer and said insulator down to said etch stop layer.

12. The method of claim 11 including selectively removing the exposed portion of said etch stop layer over said dielectric layer.

13. A phase change memory comprising:

a substrate;

an electrode on said substrate;

an insulator having a pore formed therein over said substrate, said pore extending to said electrode;

a conductive layer over said insulator;

a phase change material adhered to said insulator by said conductive layer, said phase change material in said pore; and

a dielectric layer between said phase change material and said electrode such that current between the phase change material and the electrode must pass through said dielectric layer.

14. The memory of claim 13 including a breakdown channel in said dielectric material.

15. The memory of claim 13 wherein said dielectric layer is substantially planar.

16. The memory of claim 13 wherein said dielectric layer is generally u-shaped and lines said pore.

17. The memory of claim 13 wherein said conductive layer includes titanium.

18. A system comprising:

a substrate;

a phase change memory formed on the substrate, said memory including an electrode on said substrate and the insulator having a pore formed therein over said substrate, said pore extending to said electrode, a conductive layer over said insulator, a phase change material adhered to said insulator by said conductive layer, said phase change material in said pore and a dielectric layer between said phase change material and said electrode such that current between the phase change material and the electrode must pass through said dielectric layer; and

a battery receptacle coupled to said phase change memory.

19. The system of claim 18 including a breakdown channel in said dielectric material.

20. The system of claim 18 wherein said dielectric layer is substantially planar.

21. The system of claim 18 wherein said dielectric layer is generally U-shaped and lines said pore.

22. The system of claim 18 wherein conductive layer includes titanium.

23. The system of claim 18 including a processor coupled to said memory.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Nov 12, 2019
From: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
Reel/Frame 051028/0001 →
RELEASE OF SECURITY INTEREST Recorded Oct 9, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 050937/0001 →
RELEASE OF SECURITY INTEREST Recorded Aug 23, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: MICRON TECHNOLOGY, INC.
Reel/Frame 047243/0001 →
SECURITY INTEREST Recorded Jul 13, 2018
From: MICRON TECHNOLOGY, INC.; MICRON SEMICONDUCTOR PRODUCTS, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 047540/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE REPLACE ERRONEOUSLY FILED PATENT #7358718 WITH THE CORRECT PATENT #7358178 PREVIOUSLY RECORDED ON REEL 038669 FRAME 0001. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Recorded Jun 8, 2017
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 043079/0001 →
PATENT SECURITY AGREEMENT Recorded Jun 2, 2016
From: MICRON TECHNOLOGY, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 038954/0001 →
SECURITY INTEREST Recorded May 12, 2016
From: MICRON TECHNOLOGY, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038669/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2012
From: INTEL CORPORATION
To: NUMONYX B.V.
Reel/Frame 028055/0625 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2011
From: NUMONYX B.V.
To: MICRON TECHNOLOGY, INC.
Reel/Frame 027075/0682 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 3, 2005
From: DENNISON, CHARLES H.
To: INTEL CORPORATION
Reel/Frame 016120/0419 →