Method of mounting wafer on printed wiring substrate
To make it possible to utilize both surfaces of a wafer, a wafer ( 1 ) is provided with a through hole ( 2 ) between upper and lower surfaces, an insulating layer ( 14 ) is formed in an inner surface of the through hole ( 2 ), rewiring circuits ( 3, 4 ) are formed on both the upper and lower surfaces, the rewiring circuits ( 3, 4 ) are connected by a plating ( 9 ) applied on the insulating layer ( 14 ) within the through hole ( 2 ), thermal stress relaxing posts ( 5, 6 ) are formed on the rewiring circuits ( 3, 4 ) by a conductive material such as a solder bumps ( 7, 8 ) are formed on the thermal stress relaxing posts ( 5, 6 ), and the solder bump ( 7 ) or ( 8 ) is connected to a wiring circuit ( 12 ) of a printed wiring substrate ( 11 ).
1. A method of mounting a wafer to a printed wiring substrate comprising the steps of:
providing a through hole between upper and lower surfaces in a wafer;
forming rewiring circuits on both upper and lower surfaces respectively in accordance with a plating;
forming a thermal stress relaxing post on said rewiring circuit in the upper surface side by a conductive material;
forming a solder bump on said thermal stress relaxing post;
forming an output terminal on said rewiring circuit in the lower surface side;
connecting the rewiring circuits on said upper and lower surfaces to each other by a plating applied within said through hole; and
bonding the output terminal of said wafer to the rewiring circuit of the printed wiring substrate.
2. A method of mounting a wafer to a printed wiring substrate comprising the steps of:
providing a through hole between upper and lower surfaces in a wafer;
forming an insulating layer on an inner surface of said through hole;
forming rewiring circuits on both upper and lower surfaces respectively in accordance with a plating;
forming a thermal stress relaxing post on said rewiring circuit by a conductive material;
forming a solder bump on said thermal stress relaxing post;
connecting the rewiring circuits on said upper and lower surfaces to each other by a plating applied on the insulating layer within said through hole; and
bonding the solder bump of said wafer to the rewiring circuit of the printed wiring substrate.
3. A method of mounting a wafer to a printed wiring substrate comprising the steps of:
providing a through hole between upper and lower surfaces in a wafer;
forming an insulating layer on an inner surface of said through hole;
forming rewiring circuits on both upper and lower surfaces respectively in accordance with a plating;
forming a thermal stress relaxing post on said rewiring circuit in the upper surface side by a conductive material;
forming a solder bump on said thermal stress relaxing post;
forming an output terminal in said rewiring circuit in the lower surface side;
connecting the rewiring circuits on said upper and lower surfaces to each other by a plating applied on the insulating layer within said through hole; and
bonding the outer terminal of said wafer to the rewiring circuit of the printed wiring substrate.
4. A method of mounting a wafer to a printed wiring substrate as claimed in claim 1 , wherein a plurality of through holes are provided lengthwise and breadthwise in a grid shape on one wafer, the rewiring circuit is formed in each of portions surrounded by the plurality of through holes, and the wafer is cut at positions of the plurality of through holes.
5. A method of mounting a wafer to a printed wiring substrate as claimed in claim 2 , wherein a plurality of through holes are provided lengthwise and breadthwise in a grid shape on one wafer, the rewiring circuit is formed in each of portions surrounded by the plurality of through holes, and the wafer is cut at positions of the plurality of through holes.
6. A method of mounting a wafer to a printed wiring substrate as claimed in claim 3 , wherein a plurality of through holes are provided lengthwise and breadthwise in a grid shape on one wafer, the rewiring circuit is formed in each of portions surrounded by the plurality of through holes, and the wafer is cut at positions of the plurality of through holes.