Method for forming a storage cell capacitor compatible with high dielectric constant materials
An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.
1. A method for fabricating an integrated circuit structure on a substrate, comprising:
forming an insulative layer on the substrate;
forming a first opening in the insulative layer;
forming digit lines in the first opening;
forming a second opening in the insulative layer; and
forming an electrode, wherein forming the electrode includes:
forming a first portion of the electrode in a lower region of the second opening;
forming a second portion of the electrode in the second opening and overlying the first portion, said insulative layer encompassing a sidewall of said second portion;
forming a third portion of the electrode overlying the second portion and overlying at least a portion of the insulative layer, wherein said first portion and said second portion are different materials; and
forming a dielectric layer on the third portion, with the dielectric layer including a material from a group of materials consisting of Bax Sr(1−x) TiO 3 , BaTiO 3 , SrTiO 3 , PbTiO 3 , Pb(Zr,Ti)O 3 , (Pb,La)(Zr,Ti)O 3 , (Pb,La)TiO 3 , KNO 3 , and LiNbO 3 .
2. The method of claim 1 , wherein said second portion and said third portion are different materials.
3. The method of claim 2 , wherein said first portion and said third portion are different materials.
4. A method for fabricating an electrode, comprising:
forming an insulative layer on a substrate;
forming buried digit lines in the insulative layer;
forming an opening in the insulative layer;
forming a first portion of an electrode in a lower region of the opening;
forming a second portion of the electrode in the opening and overlying the first portion, said insulative layer encompassing a sidewall of said second portion;
forming a third portion of the electrode overlying the second portion and extending above a top surface of the insulative layer, wherein said first portion and said second portion are different materials; and
forming a dielectric layer on the third portion, with the dielectric layer including a material from a group of materials consisting of Bax Sr (1−n) , TiO 3 , BaTiO 3 , SrTiO 3 , PbTiO 3 , Pb(Zr,Ti)O 3 , (Pb,La)(Zr,Ti)O 3 , (Pb,La)TiO 3 , KNO 3 , and LiNbO 3 .
5. The method of claim 4 , wherein said second portion and said third portion are different materials.
6. The method of claim 5 , wherein said first portion and said third portion are different materials.
7. The method of claim 4 , wherein forming said insulative layer further comprises:
depositing a first portion of said insulative layer to overlie said substrate; and
depositing a second portion of said insulative layer to overlie said first portion of said insulative layer, said second portion of said insulative layer having oxidation resistant properties.
8. The method of claim 7 , wherein forming said insulative layer further comprises:
patterning said second portion of said insulative layer to define the opening; and
removing exposed regions of said first and second portions of said insulative layer to create the opening.
9. The method of claim 7 , wherein forming said insulative layer further comprises planarizing said first portion of said insulative layer.
10. A method for fabricating an electrode, comprising:
forming an insulative layer on a substrate;
forming an opening in the insulative layer;
forming digit lines in the opening;
forming a first portion of an electrode in a lower region of the opening, wherein the first portion includes silicon;
forming a second portion of the electrode in the opening and overlying the first portion, said insulative layer encompassing a sidewall of said second portion; and
forming a third portion of the electrode overlying the second portion and overlying at least a portion of the insulative layer, wherein said first portion and said second portion are different materials.
11. The method of claim 10 , wherein said second portion and said third portion are different materials.
12. The method of claim 11 , wherein said first portion and said third portion are different materials.
13. A method for fabricating an integrated circuit electrode, comprising:
forming an insulative layer on a substrate, the insulative layer having a top surface;
forming an opening in the insulative layer;
forming digit lines in the opening;
forming a first portion of an electrode in a lower region of the opening, wherein the first portion includes silicon;
forming a second portion of the electrode in the opening and overlying the first portion and extending above the top surface of the insulative layer such that said insulative layer encompasses a sidewall of said second portion;
forming a third portion, materially different than the first portion, of the electrode in the opening and overlying the second portion; and
forming a fourth portion of the electrode overlying the third portion.
14. The method of claim 10 , wherein forming the third layer includes encompassing a lower sidewall of the third portion with said insulative layer.
15. The method of claim 13 , wherein said third portion and said fourth portion are different materials.
16. The method of claim 15 , wherein said second portion and said fourth portion are different materials.
17. The method of claim 16 , wherein the second or third portion is a diffusion barrier layer and the fourth portion is an oxidation resistant layer.