Reduced turn-on current content addressable memory (CAM) device and method
View Patent ↗A content addressable memory (CAM) device ( 400 ) can sequentially apply command and key data to different sections ( 404 - 1 to 404 - 4 ). Within each section, CAM cores ( 402 - 11 to 402 - 44 ) can be sequentially activated. Current surges when transitioning from an idle state to an active state, or vice versa, can be significantly reduced with additional latency but no loss in throughput.
1. A content addressable memory (CAM) device, comprising:
a plurality of sections, each section including a plurality of blocks, each block including a plurality of CAM entries and having an active mode and an idle mode, the active mode consuming more current than the idle mode;
a first control circuit that sequentially applies command data to the sections; and
a second control circuit that activates the blocks in each section in a sequential fashion.
2. The CAM device of claim 1 , wherein:
the each block enters the active mode in response to at least a search command.
3. The CAM device of claim 1 , wherein:
the first control circuit applies command and search data to the sections according to a periodic signal.
4. The CAM device of claim 3 , wherein:
the periodic signal has a period T; and
the second control circuit sequentially activates all blocks in a given section within the period T.
5. The CAM device of claim 3 , wherein:
the second control circuit sequentially activates all blocks in a given section within the period ½ T.
6. The CAM device of claim 1 , wherein:
the plurality of sections includes a first section and at least one subsequent section; and
the first control circuit comprises a command and data register coupled to an input of each subsequent section, the command and data registers being commonly controlled by timing signal.
7. The CAM device of claim 1 , wherein:
the plurality of blocks within each section include a first block and at least one subsequent block; and
the second control circuit comprises a delay circuit having an output coupled to each subsequent block arranged in series, with a first delay circuit in the series receiving a timing signal.
8. The CAM device of claim 7 , wherein:
the first control circuit sequentially applies command and search data to the sections according to a periodic clock signal; and
the second control circuit receives the periodic signal as the timing signal.
9. The CAM device of claim 8 , wherein:
the periodic clock signal has a period T; and
each delay circuit delays the periodic clock signal by no more than ⅛ T.
10. The CAM device of claim 1 , further including:
each section provides section results on a corresponding output bus;
a result logic circuit that generates an overall device result from the section results; and
an output synchronizing circuit coupled to each output bus that provides section results of each section to the result logic circuit.
11. The CAM device of claim 10 , wherein:
the plurality of sections have an order corresponding to the order in which command and search data is received; and
the output synchronizing circuit comprises a clocked output path corresponding to at least a first section and a subsequent section, the clocked output path corresponding to the first section having a plurality of result registers arranged in series between the output bus of the first section and the result logic circuit, the clocked output paths for subsequent sections having a smaller number of result registers according to the order of the sections.
12. A content addressable memory (CAM) device, comprising:
a plurality of blocks logically arranged into matrix of rows and columns, each block including a plurality of CAM entries that each search operation compares a stored data value with an applied search key;
a first control circuit that sequentially activates columns of blocks in response to the same search command; and
a second control circuit that sequentially activates rows of blocks in response to the same search command.
13. The CAM device of claim 12 , wherein:
the matrix of blocks includes a first column having a column input coupled to a first input bus and a plurality of subsequent columns;
the first control circuit comprises a plurality of command data registers coupled in series with one another, including a first command data register having an input coupled to the first input bus, each command data register having an output coupled to one of the subsequent columns; and
the second control circuit comprises a plurality of delay circuits coupled in series with one another, including a first delay circuit having an input coupled to a clock signal, and a plurality of subsequent delay circuits, each delay circuit having an output coupled to one of the rows.
14. A method of activating a content addressable memory (CAM) device in response to a command, comprising the steps of:
receiving a predetermined CAM operation command;
sequentially applying command data to multiple sections of the CAM device; and
sequentially activating multiple blocks within each section.
15. The method of claim 14 , wherein:
the predetermined CAM operation command comprises a search command and search key data.
16. The method of claim 14 , wherein:
the step of sequentially applying command data to multiple sections includes
applying command data to first section, and
applying command data to a subsequent section after all of the multiple blocks of a previous section have been sequentially activated to process the same command data.
17. The method of claim 14 , wherein:
the step of sequentially applying command data to multiple sections of the CAM device includes applying command data on subsequent edges of a periodic clock signal.
18. The method of claim 14 , wherein:
the step of sequentially activating multiple blocks within each section includes
generating a plurality of block activation signals by delaying the periodic clock signal by increasingly larger amounts, and
activating each block according to a different block activation signal.
19. The method of claim 14 , wherein:
the number of blocks in each section is N;
the periodic signal as a period T; and
the block activation signals are delayed by an amount no more than T/N.
20. The method of claim 14 , wherein:
the number of blocks in each section is N;
the periodic signal as a period T; and
the block activation signals are delayed by an amount no more than T/(2N).