Device package and method for the fabrication and testing thereof
View Patent ↗Provided are methods of forming sealed via structures. One method involves: (a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface; (b) forming a layer on the first surface of the substrate; (c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface; (d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and (e) providing a conductive structure for sealing the via structure. Also provided are sealed via structures, methods of detecting leakage in a sealed device package, sealed device packages, device packages having cooling structures, and methods of bonding a first component to a second component.
1. A method of forming a sealed via structure, comprising:
(a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface;
(b) forming a layer on the first surface of the substrate;
(c) etching a via hole through the substrate from the second surface to the layer, the via hole having a first perimeter at the first surface;
(d) forming an aperture in the layer, wherein the aperture has a second perimeter within the first perimeter; and
(e) providing a conductive structure for sealing the via structure.
2. A method of forming a sealed via structure, comprising:
(a) providing a semiconductor substrate having a first surface and a second surface opposite the first surface;
(b) forming an insulating layer on the first surface of the substrate;
(c) etching a via hole through the substrate from the second surface to the insulating layer;
(d) forming an aperture in the layer; and
(e) providing a metallization structure for sealing the via structure.
3. The method of claim 1 , wherein (d) comprises forming a plurality of apertures in the layer, wherein each aperture has a second perimeter within the first perimeter.
4. The method of claim 1 , wherein the semiconductor substrate is a silicon wafer or a grid of die removed from a silicon wafer.
5. The method of claim 1 , wherein the layer is an insulating layer.
6. The method of claim 5 , wherein the insulating layer is a silicon nitride layer.
7. The method of claim 1 , wherein a layer is formed on the second surface of the substrate when forming the layer in (b), the method further comprising: patterning the layer on the second surface of the substrate, wherein the patterned layer forms an etching mask for the via hole etching of (c).
8. The method of claim 1 , further comprising forming an insulating layer in the via hole.
9. The method of claim 8 , wherein the metallization structure comprises a metal layer formed over the insulating layer in the via hole.
10. The method of claim 1 , wherein the metallization structure comprises a plurality of conductive lines.
11. The method of claim 1 , wherein (e) is conducted subsequent to (d).
12. The method of claim 1 , wherein (d) is conducted subsequent to (e).
13. The method of claim 1 , wherein the layer comprises an etch stop layer.
14. The method of claim 13 , further comprising forming a membrane layer over the etch stop layer.
15. The method of claim 14 , wherein the aperture is formed through the layer and the membrane layer.
16. The method of claim 15 , wherein a plurality of the apertures are formed through the layer and the membrane layer.
17. The method of claim 16 , further comprising forming a dielectric layer on the sidewalls of the apertures.
18. The method of claim 16 , wherein the metallization structure comprises conductive plugs in the apertures.
19. The method of claim 14 , wherein the membrane layer comprises a silicon nitride layer.
20. The method of claim 1 , wherein the metallization structure comprises a conductive line for providing electrical connection to a device mounted on the second surface of the semiconductor substrate.