Method and structures for testing a semiconductor wafer prior to performing a flip chip bumping process
View Patent ↗An interface assembly ( 20 ) and method for testing a semiconductor wafer prior to performing a flip chip bumping process are provided. The interface assembly includes a flip chip bonding pad ( 24 ) having a region ( 28 ) for performing the bumping process. A test pad ( 22 ) is integrally constructed with the bonding pad and includes a probe region ( 26 ) for performing wafer-level testing prior to performing the bumping process. The integral construction of the bonding and testing pads avoids, for example, an introduction of propagation delays to test signals passing therethrough, thereby improving the accuracy and reliability of wafer test results.
1. An interface assembly for a semiconductor wafer, said interface assembly comprising:
a flip chip bonding pad including a region for performing a bumping process; and
a test pad integrally constructed with said bonding pad that form an integral conductive structure such that separate interconnect testing lines from said test pad to said bonding pad are not present in said integral structure, said test pad being coplanar relative to said flip chip bonding pad and including a probe region for performing wafer-level testing prior to performing said bumping process.
2. The interface assembly of claim 1 wherein said test pad may be disposed anywhere along a periphery of said bonding pad.
3. The interface assembly of claim 1 wherein said bonding pad comprises a shape selected from the group consisting of a polygonal shape, and a circular shape.
4. The interface assembly of claim 1 wherein said test pad comprises a shape selected from the group consisting of a polygonal shape, and a circular shape.
5. The interface assembly of claim 1 further comprising a first metal redistribution layer electrically connected to said bonding and test pads, and being co-planar with one another.
6. The interface assembly of claim 5 wherein said first metal redistribution layer is electrically connected by way of a via to a second redistribution layer being disposed in a different plane than the first redistribution layer.
7. The interface assembly of claim 1 wherein the region to be bumped is defined by a first opening in a passivation layer.
8. The interface assembly of claim 7 wherein the probe region is defined by a second opening in said passivation layer, said first and second openings being spaced apart from one another.
9. A method for testing a semiconductor wafer prior to performing a flip chip bumping process, said method comprising:
providing a flip chip bonding pad having a region for performing said bumping process; integrally constructing a test pad with said bonding pad to form an integral conductive structure such that separate interconnect testing lines from said test pad to said bonding pad are not present in said integral structure; and
disposing said test pad coplanar with said flip chip bonding pad, said test pad including a probe region for performing a wafer test prior to performing said bumping process.
10. An interface assembly for a semiconductor wafer, said interface assembly comprising:
a flip chip bonding pad including a region for performing a bumping process;
a test pad integrally constructed with said bonding pad, said test pad being coplanar relative to said flip chip bonding pad and including a probe region for performing wafer-level testing prior to performing said bumping process; and
a first metal redistribution layer electrically connected to said bonding and test pads, and being co-planar with one another, said first metal redistribution layer is electrically connected by way of a via to a second redistribution layer being disposed in a different plane than the first redistribution layer.