Fuse memory cell comprising a diode, the diode serving as the fuse element
A memory cell is formed of a semiconductor junction diode interposed between conductors. The cell is programmed by rendering the memory cell very high-resistance, such that current no longer flows between the conductors on application of a read voltage. In this cell the diode behaves as a fuse. The semiconductor junction diode comprises silicon, the silicon crystallized in contact with a silicide. The silicide may provide a template for crystallization, decreasing the defect density of the silicon and improving its conductivity. It is advantageous to reduce a dielectric layer (such as an oxide, nitride, or oxynitride) intervening between the silicon and the silicon-forming metal during the step of forming the silicide.
1 . A nonvolatile fuse memory cell having an unprogrammed and a programmed state, comprising a semiconductor junction diode, wherein the semiconductor junction diode operates as a fuse when the cell is converted from the unprogrammed state to the programmed state.
2 . The nonvolatile fuse memory cell of claim 1 wherein, in the unprogrammed state, the semiconductor junction diode is in a low-impedance state, and in the programmed state, the semiconductor junction diode is in a high-impedance state.
3 . The nonvolatile fuse memory cell of claim 2 further comprising a first conductor and a second conductor, wherein, in the unprogrammed state, the semiconductor junction diode is disposed between and is in electrical contact with the first and second conductors.
4 . The nonvolatile fuse memory cell of claim 3 wherein, in the unprogrammed, low-impedance state, upon application of a read voltage between the first and second conductors of between about 0.5 and about 3 volts, a current of about 0.4 microamps or more flows between the first and second conductors.
5 . The nonvolatile fuse memory cell of claim 4 wherein, in the unprogrammed, low-impedance state, upon application of a read voltage between the first and second conductors of between about 0.5 and about 3 volts, a current of about 1.0 microamps or more flows between the first and second conductors.
6 . The nonvolatile fuse memory cell of claim 3 wherein, in the programmed, high-impedance state, the resistance across the diode is about 1×10 7 ohms or more.
7 . The nonvolatile fuse memory cell of claim 6 wherein, in the programmed, high-impedance state, the resistance across the diode is about 2×10 8 ohms or more.
8 . The nonvolatile fuse memory cell of claim 3 wherein the first conductor is formed at a first height above a substrate, the second conductor is formed at a second height above a substrate, the second height above the first, and the semiconductor junction diode is a vertically oriented pillar.
9 . The nonvolatile fuse memory cell of claim 8 wherein the semiconductor junction diode is a p-i-n diode.
10 . The nonvolatile fuse memory cell of claim 9 wherein, in the unprogrammed state, the semiconductor junction diode is in contact with a silicide layer.
11 . The nonvolatile fuse memory cell of claim 10 wherein the silicide layer comprises a silicide selected from a group consisting of titanium silicide, cobalt silicide, chromium silicide, tantalum silicide, platinum silicide, nickel silicide, niobium silicide, and palladium silicide.
12 . The nonvolatile fuse memory cell of claim 11 wherein the first conductor or the second conductor comprises tungsten.
13 . The nonvolatile fuse memory cell of claim 11 wherein the maximum diameter of the semiconductor junction diode is no more than about 150 nm.
14 . The nonvolatile fuse memory cell of claim 13 wherein the maximum diameter of the semiconductor junction diode is no more than about 90 nm.
15 . The nonvolatile fuse memory cell of claim 8 wherein the substrate comprises monocrystalline silicon.
16 . The nonvolatile fuse memory cell of claim 2 wherein the semiconductor junction diode is converted from the unprogrammed low-impedance state to the programmed high-impedance state by application of a programming voltage across the diode.
17 . The nonvolatile fuse memory cell of claim 16 wherein the programming voltage is between about 4 and about 30 volts.
18 . The nonvolatile fuse memory cell of claim 2 wherein the memory cell resides in a first memory level of a monolithic three dimensional memory array.
19 . The nonvolatile fuse memory cell of claim 18 wherein at least a second memory level is monolithically formed above the first memory level.
20 . A plurality of unprogrammed nonvolatile fuse memory cells comprising:
a plurality of substantially parallel first conductors formed at a first height above a substrate;
a plurality of substantially parallel second conductors formed at a second height above the substrate, wherein the second height is different from the first height;
a plurality of conductive pillars, each pillar disposed between one of the first conductors and one of the second conductors, and each pillar in electrical contact with one of the first pillars and one of the second pillars,
wherein each pillar comprises a silicide layer.
21 . The plurality of unprogrammed nonvolatile fuse memory cells of claim 20 wherein each of the plurality of pillars comprises a semiconductor junction diode.
22 . The plurality of unprogrammed nonvolatile fuse memory cells of claim 21 wherein each silicide layer is between and in contact with one of the semiconductor junction diodes and one of the second plurality of conductors.
23 . The plurality of unprogrammed nonvolatile fuse memory cells of claim 22 wherein the second height is above the first height.
24 . The plurality of unprogrammed nonvolatile fuse memory cells of claim 23 wherein each of the nonvolatile fuse memory cells comprises:
a portion of one of the plurality of first conductors;
one of the plurality of pillars; and
a portion of one of the plurality of second conductors.
25 . The plurality of unprogrammed nonvolatile fuse memory cells of claim 24 wherein for each of the unprogrammed memory cells, upon application of a read voltage between the first conductor and the second conductor of a memory cell of between about 0.5 and about 3 volts, a current between about 0.4 and about 100 microamps flows between the first conductor and the second conductor of that memory cell.
26 . The plurality of unprogrammed nonvolatile fuse memory cells of claim 25 wherein for each of the unprogrammed memory cells, upon application of a read voltage between the first conductor and the second conductor of a memory cell of between about 1.3 and about 2.3 volts, a current between about 1 and about 50 microamps flows between the first conductor and the second conductor of that memory cell.
27 . The plurality of unprogrammed nonvolatile fuse memory cells of claim 20 wherein the silicide layer comprises a silicide selected from a group consisting of titanium silicide, cobalt silicide, chromium silicide, tantalum silicide, platinum silicide, nickel silcide, niobium silicide, and palladium silicide.
28 . The plurality of unprogrammed nonvolatile fuse memory cells of claim 20 wherein the substrate comprises monocrystalline silicon.
29 . The plurality of unprogrammed nonvolatile fuse memory cells of claim 20 wherein the plurality of cells make up a portion of a monolithic three dimensional memory array.
30 . The plurality of unprogrammed nonvolatile fuse memory cells of claim 29 wherein the three dimensional monolithic memory array comprises at least two memory levels monolithically formed above one another.
31 . A monolithic three dimensional memory array of memory cells, the array comprising:
a first memory level, the first memory level comprising a first plurality of memory cells, each memory cell of the first plurality having an unprogrammed and a programmed state, each memory cell comprising a semiconductor junction diode, wherein the semiconductor junction diode operates as a fuse when the cell is converted from the unprogrammed state to the programmed state; and
a second memory level, the second memory level monolithically formed above the first.
32 . The monolithic three dimensional memory array of claim 31 wherein, in the unprogrammed state, each semiconductor junction diode is in a low-impedance state, and in the programmed state, each semiconductor junction diode is in a high-impedance state.
33 . The monolithic three dimensional memory array of claim 32 further wherein the first memory level further comprises a plurality of first conductors formed at a first height above a substrate and a plurality of second conductors formed at a second height above the substrate, wherein the second height is different from the first.
34 . The monolithic three dimensional memory array of claim 33 wherein each memory cell further comprising a portion of one of the first conductors and a portion of one of the second conductors, wherein, when the cell is in the unprogrammed state, the semiconductor junction diode is disposed between and is in electrical contact with the first and second conductor portions.
35 . The monolithic three dimensional memory array of claim 34 wherein, in the unprogrammed, low-impedance state, upon application of a read voltage between the first and second conductors of each memory cell of between about 0.5 and about 3 volts, a current of about 0.4 amps or more flows between the first and second conductors of the memory cell.
36 . The monolithic three dimensional memory array of claim 35 wherein, in the unprogrammed, low-impedance state, upon application of a read voltage between the first and second conductors of each memory cell of between about 0.5 and about 3 volts, a current of about 1.0 amps or more flows between the first and second conductors of the memory cell.
37 . The monolithic three dimensional memory array of claim 32 wherein, in the programmed, high-impedance state, the resistance across each semiconductor junction diode is about 1×10 7 ohms or more.
38 . The monolithic three dimensional memory array of claim 32 wherein, in the programmed, high-impedance state, the resistance across each semiconductor junction diode is about 2×10 8 ohms or more.
39 . The monolithic three dimensional memory array of claim 32 wherein each semiconductor junction diode is a vertically oriented pillar.
40 . The monolithic three dimensional memory array of claim 39 wherein each semiconductor junction diode is a p-i-n diode.
41 . The monolithic three dimensional memory array of claim 40 wherein, in the unprogrammed state, each semiconductor junction diode is in contact with a silicide layer.
42 . The monolithic three dimensional memory array of claim 41 wherein each silicide layer comprises a silicide selected from a group consisting of titanium silicide, cobalt silicide, chromium silicide, tantalum silicide, platinum suicide, nickel silicide, niobium silicide, and palladium silicide.
43 . The monolithic three dimensional memory array of claim 32 wherein each semiconductor junction diode is converted from the unprogrammed low-impedance state to the programmed high-impedance state by application of a programming voltage across the diode.
44 . The monolithic three dimensional memory array of claim 43 wherein the programming voltage is between about 4 and about 30 volts.
45 . The monolithic three dimensional memory array of claim 31 wherein the first memory level further comprises a second plurality of memory cells, wherein the memory cells of the second plurality are not fuse memory cells.
46 . The monolithic three dimensional memory array of claim 45 wherein each of the memory cells of the second plurality comprises a junction diode, the junction diode formed in an unprogrammed high-impedance state.
47 . A monolithic three dimensional memory array comprising:
a first memory level formed above a substrate, the first memory level comprising:
a plurality of substantially parallel lower conductors formed at a first height above the substrate;
a plurality of substantially parallel upper conductors formed at a second height above the substrate, wherein the second height is above the first height; and
a plurality of pillars, each pillar disposed between one of the first conductors and one of the second conductors,
wherein each pillar comprises a junction diode and a silicide layer,
wherein each junction diode is in electrical contact with one of the lower conductors and one of the upper conductors;
and a second memory level monolithically formed above the first.
48 . The monolithic three dimensional memory array of claim 47 wherein each silicide layer comprises a silicide selected from a group consisting of titanium silicide, cobalt silicide, chromium silicide, tantalum silicide, platinum silicide, nickel silicide, niobium silicide, and palladium silicide.
49 . The monolithic three dimensional memory array of claim 48 wherein each silicide layer is between and in contact with one of the junction diodes and one of the conductors.
50 . The monolithic three dimensional memory array of claim 49 wherein each silicide layer is between and in contact with one of the junction diodes and one of the upper conductors.
51 . The monolithic three dimensional memory array of claim 47 wherein the substrate comprises monocrystalline silicon.
52 . A method for forming and programming a fuse memory cell, the method comprising:
forming a memory cell, the memory cell comprising a semiconductor junction diode having an unprogrammed, low-impedance state; and
programming the memory cell by converting the diode to a programmed, high-impedance state.
53 . The method of claim 52 wherein the step of forming the memory cell further comprises:
forming a first conductor at a first height above a substrate; and
forming a second conductor at a second height above the substrate, wherein the second height is above the first height,
wherein the semiconductor junction diode is disposed between the first and second conductors and is in electrical contact with the first and second conductors.
54 . The method of claim 53 wherein the step of programming the memory cell comprises applying a programming voltage across the semiconductor junction diode.
55 . The method of claim 54 wherein the programming voltage is between about 4 and about 30 volts.
56 . The method of claim 54 wherein, in the unprogrammed, low-impedance state, upon application of a read voltage between the first and second conductors of between about 0.5 and about 3 volts, a current of about 0.4 amps or more flows between the first and second conductors.
57 . The method of claim 56 wherein, in the unprogrammed, low-impedance state, upon application of a read voltage between the first and second conductors of between about 0.5 and about 3 volts, a current of about 1.0 amps or more flows between the first and second conductors.
58 . The method of claim 54 wherein, in the programmed, high-impedance state, the resistance across the diode is about 1×10 7 ohms or more.
59 . The method of claim 58 wherein, in the programmed, high-impedance state, the resistivity across the diode is about 2×10 8 ohms or more.
60 . The method of claim 53 wherein the step of forming the memory cell further comprises forming the semiconductor junction diode by forming a p-i-n diode.
61 . The method of claim 53 wherein the step of forming the memory cell further comprises forming the semiconductor junction diode by:
forming a first heavily doped silicon layer of a first conductivity type;
forming a second lightly or intrinsically doped silicon layer directly on the first heavily doped layer; and
forming a third heavily doped silicon layer of a second conductivity type directly on the second lightly or intrinsically doped silicon layer, the second conductivity type opposite the first.
62 . The method of claim 53 wherein the first conductor is formed in a first patterning step, the semiconductor junction diode is formed in a second patterning step, and the second conductor is formed in a third patterning step, wherein each of the first, second, and third patterning steps is a separate step.
63 . The method of claim 52 wherein the step of forming the memory cell comprises preconditioning the memory cell by applying a preconditioning voltage to place the semiconductor junction diode in the unprogrammed, low-impedance state.
64 . The method of claim 63 wherein the step of programming the memory cell comprises applying a programming voltage to place the semiconductor junction diode in the programmed, high-impedance state.
65 . The method of claim 64 wherein preconditioning voltage is less than the programming voltage.
66 . The method of claim 65 wherein the preconditioning voltage is between about 3 and about 8 volts and the programming voltage is between about 7 and about 30 volts.
67 . The method of claim 52 wherein the memory cell resides in a first memory level of a monolithic three dimensional memory array.
68 . The method of claim 67 wherein at least a second memory level is monolithically formed above the first memory level.
69 . A method for forming a plurality of unprogrammed fuse memory cells, the method comprising:
forming a plurality of substantially parallel first conductors at a first height above a substrate;
forming a plurality of first semiconductor junction diodes, each first semiconductor junction diode on and in electrical contact with one of the first conductors;
forming a silicide layer on and in contact with each of the first semiconductor junction diodes; and
forming a plurality of substantially parallel second conductors at a second height above the substrate, each silicide layer in electrical contact with one of the second conductors.
70 . The method of claim 69 wherein the step of forming a silicide layer comprises:
forming an oxide region on each of the first semiconductor junction diodes;
depositing a silicide-forming metal on each oxide region; and
annealing to substantially entirely reduce each oxide region between the silicide-forming metal and the one of the first semiconductor junction diode and to form the silicide layer.
71 . The method of claim 70 wherein the silicide-forming metal is selected from a group consisting of titanium, cobalt, chromium, tantalum, platinum, nickel, niobium, and palladium.
72 . The method of claim 69 wherein the first conductors are formed in a first patterning step, the first semiconductor junction diodes are formed in a second patterning step, and the second conductors are formed in a third patterning step, wherein each of the first, second, and third patterning steps is a separate step.
73 . The method of claim 69 wherein a plurality of second semiconductor junction diodes is formed above the second conductors.
74 . The method of claim 73 wherein a plurality of third conductors is formed above the second semiconductor junction diodes.
75 . A method for forming a monolithic three dimensional memory array, the method comprising:
forming a first memory level of memory cells by a method comprising:
forming a plurality of substantially parallel lower conductors at a first height above a substrate;
forming a plurality of substantially parallel upper conductors at a second height above the substrate, the second height above the first; and
forming a plurality of pillars, each pillar disposed between and in electrical contact with one of the first conductors and one of the second conductors,
wherein each pillar comprises a silicide layer;
and monolithically forming a second memory level above the first.
76 . The method of claim 75 wherein each of the silicide layers comprises a silicide selected from a group consisting of titanium silicide, cobalt silicide, chromium silicide, tantalum silicide, platinum silicide, nickel silicide, niobium silicide, and palladium silicide.
77 . The method of claim 76 wherein each pillar comprises a semiconductor junction diode.
78 . The method of claim 77 wherein each silicide layer is formed by a method comprising:
forming an oxide region on each semiconductor junction diode;
depositing a silicide-forming metal on each oxide region; and
annealing to reduce the oxide region and to form the suicide layer.
79 . The method of claim 75 wherein the step of forming the lower conductors comprises:
depositing a first conductive material;
patterning and etching the first conductive material to form the first conductors separated by first gaps;
filling the first gaps with a first dielectric material.
80 . The method of claim 79 wherein the step of forming the pillars comprises:
depositing a semiconductor layer stack on the first conductors and first dielectric material;
patterning and etching the semiconductor layer stack to form the pillars.