Granted Patent B2

US 7,099,792 · App. 10/956,549 · Granted Aug 29, 2006

Abstract

Claims (30)

1. An apparatus having a plurality of test modules connected to a bus for testing an electronic device and responsive to a trigger transmitted on the bus, comprising:

a first test module having a programmable device programmed to execute a test sequence that includes a conditional part that is not executed until the trigger is received and to delay the execution of the conditional part after the trigger is received by a first delay amount;

a second test module having a programmable device programmed to execute a test sequence that includes a conditional part that is not executed until the trigger is received and to delay the execution of the conditional part after the trigger is received by a second delay amount; and

a third test module having a programmable device programmed to issue a request to transmit the trigger on the bus.

2. The apparatus according to claim 1 , wherein the first delay amount is larger than a second delay amount by an amount that is equal to a difference in pipeline delays of the programmable devices.

3. The apparatus according to claim 1 , wherein the test sequences executed by the programmable devices have different test periods.

4. The apparatus according to claim 3 , wherein test signals generated by the first test module upon execution of the conditional part and test signals generated by the second test module upon execution of the condition part arrive at the electronic device at the same time and at the beginning of their respective test periods.

5. The apparatus according to claim 4 , wherein each of the programmable devices includes a counter based on which the first delay amount and the second delay amount are adjusted.

6. The apparatus according to claim 1 , wherein the programmable device of the third test module is further programmed to execute a test sequence and the request to transmit the trigger on the bus is issued when test signals generated upon execution of the test sequence arrive at the electronic device.

7. The apparatus according to claim 1 , wherein the programmable device of the third test module is further programmed to strobe response signals from the electronic device and the request to transmit the trigger on the bus is issued when a predetermined event is detected in the response signals from the electronic device.

8. A test instrument for a test apparatus having a plurality of test instruments that are synchronized to a global clock and connected to a bus, comprising:

a first programmable device interfaced with the bus; and

a second programmable device coupled with the first programmable device and to a device under test, the second programmable device being programmed to execute a test sequence in response to a trigger at a rate equal to a clock speed of the device under test and to delay the trigger by a first delay amount that is defined with respect to the clock speed of the device under test,

wherein the first programmable device is programmed to pass on a tripper appearing on the bus to the second programmable device and to delay the passing of the trigger by a second delay amount that is defined with respect to the global clock speed.

9. The test instrument according to claim 8 , wherein the first delay amount is defined as the number of clock periods of the device under test.

10. The test instrument according to claim 8 , wherein the second programmable device is further programmed to issue a request for transmission of a trigger onto the bus and to delay the request by a third delay amount that is defined with respect to the global clock speed.

11. The test instrument according to claim 10 , wherein the third delay amount is an offset value equal to a predetermined base delay minus an actual delay corresponding to hardware overhead related to providing the trigger request to the first programmable device.

12. The test instrument according to claim 8 , wherein the second delay amount is an offset value equal to a predetermined base delay minus an actual delay corresponding to hardware overhead related to receiving the trigger from the first programmable device.

13. A method of synchronizing the execution of test patterns by first and second test instruments during testing of an electronic device, comprising the steps of:

initiating an instruction loop in both instruments;

receiving at both instruments a trigger to exit the instruction loop;

delaying the trigger by a first delay amount in the first test instrument and by a second delay amount in the second test instrument;

exiting the instruction loop in the first test instrument after the first delay amount and exiting the instruction loop in the second test instrument after the second delay amount;

executing the test patterns to generate test signals at the first and second test instruments; and

supplying the test signals generated at the first test instrument to the input of the electronic device and the test signals generated at the second test instrument to the input of the electronic device.

14. The method according to claim 13 , wherein the first delay amount is larger than a second delay amount by an amount that Is equal to a difference in pipeline delays of the two test instruments.

15. The method according to claim 13 , wherein the test signals generated at the first and second test instruments have different test periods.

16. The method according to claim 15 , wherein the test signals generated at the first test instrument and the test signals generated at the second test instrument are supplied to the input of the electronic device at the same time and at the beginning of their respective periods.

17. The method according to claim 13 , wherein the instruction loop comprises a wait for trigger instruction.

18. The method according to claim 13 , wherein the instruction loop comprises a series of instructions that are executed.

Assignments (8)