Leadless plastic chip carrier with contact standoff
View Patent ↗A process for fabricating a leadless plastic chip carrier. A first surface of a leadframe strip is selectively etched to thereby provide depressions in the first surface and metal contacts are deposited in the depressions in the first surface of the leadframe strip. At least one layer of metal is selectively plated on at least the metal contacts to provide a plurality of selectively plated contact pads and a die attach pad. A semiconductor die is mounted on the first surface of the die attach pad and the semiconductor die is wire bonded to ones of the contact pads. The wire bonds and the semiconductor die are encapsulated in a molding material such that the molding material covers the die attach pad and the contact pads. The leadframe strip is etched away thereby exposing the metal contacts in the form of an array and the leadless plastic chip carrier is singulated from other leadless plastic chip carriers.
1. A process for fabricating a leadless plastic chip carrier, comprising:
selectively etching a first surface of a single layer leadframe strip to thereby provide depressions in said first surface;
depositing metal contacts in said depressions by applying a soldering paste on a bare surface of the single layer leadframe strip from which an etching material has been removed, the bare surface being said first surface of said leadframe strip having said depressions formed therein;
selectively plating at least one layer of metal on at least said metal contacts to provide a plurality of selectively plated contact pads and a die attach pad;
mounting a semiconductor die on said first surface of said die attach pad;
wire bonding said semiconductor die to ones of the contact pads;
encapsulating said wire bonds and the semiconductor die in a molding material such that said molding material covers the die attach pad and the contact pads;
etching away said leadframe strip thereby exposing said metal contacts in the form of an array; and
singulating said leadless plastic chip carrier from other leadless plastic chip carriers.
2. The process according to claim 1 , wherein said selectively plating comprises selectively plating a plurality of layers of metal on at least said metal contacts.
3. The process according to claim 2 , wherein said plurality of layers of metal includes successive layers of gold, nickel, copper, nickel and gold.
4. The process according to claim 2 , wherein said plurality of layers of metal includes successive layers of nickel, palladium and gold.
5. The process according to claim 2 , wherein said plurality of layers of metal includes successive layers of palladium and gold.
6. The process according to claim 2 , wherein said plurality of layers of metal includes successive layers of palladium, nickel, palladium and gold.
7. The process according to claim 2 , wherein said plurality of layers of metal includes successive layers of palladium, nickel and silver.
8. The process according to claim 2 , wherein said plurality of layers of metal includes successive layers of copper, nickel and gold.
9. The process according to claim 1 , wherein said selectively etching comprises selectively etching to provide a plurality of depressions for depositing a plurality of metal contacts on which said die attach pad is selectively plated.
10. The process according to claim 1 , wherein said selectively etching comprises selectively etching to provide a large depression for depositing a large metal contact on which said die attach pad is selectively plated, said large depression being circumscribed by at least one row or smaller depressions.
11. The process according to claim 1 , wherein said depositing metal contacts in said depressions comprises solder paste printing and reflowing to provide said metal contacts.
12. The process according to claim 1 , wherein said selectively etching comprises:
applying a layer of etch resist to said leadframe strip;
patterning said etch resist to expose selected portions of the first surface of the leadframe strip; and
etching said selected portions of said first surface of said leadframe strip.
13. The process according to claim 12 , wherein said selectively etching further comprises:
removing a remainder of said etch resist.
14. The process according to claim 1 , wherein selectively plating comprises:
depositing a plating mask on said first surface of said leadframe strip and said metal contacts;
imaging and developing said mask to expose at least a surface of said metal contacts at removed portions of said mask;
plating at least one metal layer on said surface of said metal contacts at the removed portions of said mask; and
removing a remainder of said plating mask.
15. The process according to claim 14 , wherein a portion of said leadframe strip is exposed during imaging and developing said mask, said die attach pad being plated up on said portion of said leadframe strip.
16. The process according to claim 1 , further comprising wire bonding said semiconductor die to said die attach pad prior to encapsulating.