Flash memory devices and methods of fabricating the same
View Patent ↗Flash memory devices and methods of fabricating the same are disclosed. A disclosed method comprises doping at least one active region of a substrate, and forming an etching mask layer on the active region. The etching mask layer defines an opening exposing a portion of the active region. The disclosed method further comprises forming an etching groove in the active region. The etching groove separates a source region and a drain region. The disclosed method also comprises growing an epitaxial layer within the etching groove; forming a gate insulating layer on the epitaxial layer; depositing a first polysilicon layer on inner sidewalls of the opening and on the gate insulating layer; forming a dielectric layer on the first polysilicon layer; and depositing a second polysilicon layer on the dielectric layer.
1. A method of fabricating a flash memory device comprising:
doping at least one active region of a substrate;
forming an etching mask layer on the active region, the etching mask layer defining an opening exposing a portion of the active region;
forming an etching groove in the exposed portion of the active region, the etching groove separating a source region and a drain region;
growing an epitaxial layer within the etching groove;
forming a gate insulating layer within the opening, the gate insulating layer being formed on the epitaxial layer;
depositing a first polysilicon layer on inner sidewalls of the opening and on the gate insulating layer;
forming a dielectric layer on the first polysilicon layer; and
depositing a second polysilicon layer on the dielectric layer.
2. A method as defined by claim 1 , wherein the etching mask layer is a single layer of oxide or a multi-layer of oxide and nitride.
3. A method of fabricating a flash memory device comprising:
depositing an insulating layer on a substrate
forming an etching mask layer defining an opening by removing a portion of the insulating layer;
forming an etching groove in an active region of the substrate exposed by the opening to define a source region and a drain region;
forming a channel layer comprising an epitaxial layer within the etching groove;
forming a gate insulating layer on the epitaxial layer;
forming a floating gate on a bottom and inner sidewalls of the opening;
forming a dielectric layer on the floating gate; and
forming a control gate on the dielectric layer.
4. A method as defined by claim 3 , wherein the dielectric layer defines a dielectric opening, and forming the control gate comprises filling the dielectric opening with the control gate.
5. A method as defined in claim 4 , wherein the dielectric opening is a generally vertical opening.
6. A method as defined in claim 5 , wherein the control gate has a T-shaped cross-section.
7. A method as defined in claim 3 , wherein the floating gate extends above the etching mask layer.