Ferromagnetic layer compositions and structures for spin polarized memory devices, including memory devices
View Patent ↗Ferromagnetic materials for use with spin memory and logic devices include a geometry and composition adapted to increase spin injection efficiency and/or reduce fringe fields. The ferromagnetic materials can be oriented to implement a variable spin resistance. The ferromagnetic layers are fabricated to permit the device to have two stable magnetization states, parallel and antiparallel. In the “on” state the device has two settable, stable resistance states determined by the relative orientation of the magnetizations of the ferromagnetic layers. An external magnetic field can change the magnetization state of the device by orienting the magnetization of the ferromagnetic layers to be parallel or antiparallel, thus changing the resistance of the device to a current of spin polarized electrons.
1. A spin polarized electron current device comprising:
a first ferromagnetic layer having a first coercivity, said first ferromagnetic layer having a first shape which includes a first curved edge followed by first straight edge;
a second ferromagnetic layer having a second coercivity larger than said first coercivity;
wherein the spin polarized electron current device is situated on a silicon substrate, such that said variable magnetic resistance varies in accordance with a relationship between a first magnetization state of said first ferromagnetic layer and a second magnetization state of said second ferromagnetic layer.
2. The spin polarized electron current device of claim 1 , wherein said first shape includes a second curved edge following said first straight edge, and a third straight edge following said second curved edge.
3. The spin polarized electron current device of claim 1 , wherein said first shape is oriented so as to reduce fringe fields.
4. The spin polarized electron current device of claim 1 , wherein said second ferromagnetic layer shape also includes a first curved edge followed by a second straight edge.
5. The spin polarized electron current device of claim 1 , wherein both said first ferromagnetic layer and said second ferromagnetic layer overly said silicon substrate.
6. The spin polarized electron current device of claim 1 , further a conduction region situated between said a first ferromagnetic layer and said second ferromagnetic layer which conduction region can be controlled to have a high impedance or a low impedance to said spin polarized current.
7. The spin polarized electron current device of claim 6 , further including a gate that controls a conductivity of said conduction region in response to a control signal applied to said gate.
8. The spin polarized electron current device of claim 7 , wherein a magnetization orientation of said first ferromagnetic layer and said second ferromagnetic layer are controlled so that said spin polarized current does not precess in response to said control signal.
9. The spin polarized electron current device of claim 6 , wherein said conduction region has a high resistance which can isolate any data stored in the device.
10. The spin polarized electron current device of claim 1 , wherein the device acts as a memory device that stores data in the form of said variable magnetic resistance to said spin polarized current.
11. The spin polarized electron current device of claim 1 , wherein the device operates as a logic gate in response to a pair of input logic signals.
12. The spin polarized electron current device of claim 1 , wherein the spin polarized electron current device is part of a read head.
13. The spin polarized electron current device of claim 1 , further including a complementary metal oxide semiconductor (CMOS) sense amplifier coupled to an said spin polarized electron current device.
14. The spin polarized electron current device of claim 1 , wherein the spin polarized electron current device is situated on a first level, and at least one second spin polarized electronic current device is stacked over said spin polarized electron current device on a second level.
15. A spin polarized electron current memory device comprising:
a first ferromagnetic layer having a first coercivity situated on a first region of a semiconductor substrate, said first ferromagnetic layer having a first shape which includes a first curved edge followed by first straight edge;
a second ferromagnetic layer having a second coercivity larger than said first coercivity situated on a second opposing region of a semiconductor substrate;
wherein the spin polarized electron current memory device is situated on a silicon substrate, and a variable magnetic resistance to a spin polarized current in a third region of said semiconductor substrate situated between first ferromagnetic layer and said second ferromagnetic layer can be measured using a read signal to determine a data value stored in the spin polarized electron current memory device;
further wherein said third region has a variable electrical conductivity which is controlled by a separate control signal;
wherein said data value is isolated by said third region having a high electrical impedance when said data is stored.
16. A spin polarized electron current device comprising:
a first ferromagnetic layer having a first coercivity;
a second ferromagnetic layer having a second coercivity larger than said first coercivity;
wherein the spin polarized electron current device is situated on a silicon substrate, and carries a spin polarized current, which varies in accordance with a relationship between a first magnetization state of said first ferromagnetic layer and a second magnetization state of said second ferromagnetic layer;
an enhancement layer situated between said ferromagnetic layer and said second ferromagnetic layer, which enhancement layer is adapted to increase a polarization efficiency for said spin polarized current.
17. The spin polarized electron current device of claim 16 , wherein said enhancement layer reduces an ohmic contact resistance between said first ferromagnetic layer and a high impedance region.
18. The spin polarized electron current device of claim 17 , wherein said enhancement layer reduces an effective length of a current path in said high impedance region.
19. The spin polarized electron current device of claim 16 , wherein a data value is stored in the device in the form of a variable magnetic resistance to said spin polarized current.
20. The spin polarized electron current device of claim 16 , wherein the spin polarized electron current device is part of a read head.
21. The spin polarized electron current device of claim 16 , further including a complementary metal oxide semiconductor (CMOS) sense amplifier coupled to an output of said spin polarized electron current device.
22. The spin polarized electron current device of claim 16 , wherein the spin polarized electron current device is situated on a first level, and at least one second spin polarized electronic current device is stacked over said spin polarized electron current device on a second level.
23. A spin polarized electron current device comprising:
a first ferromagnetic layer having a first coercivity;
a second ferromagnetic layer having a second coercivity larger than said first coercivity;
wherein at least one of said first ferromagnetic layer and said second ferromagnetic layer include a Heusler alloy adapted to inject a spin polarized current into a high electrical impedance region situated between said first ferromagnetic layer and said second ferromagnetic layer;
wherein the spin polarized electron current device is situated on a silicon substrate, and carries a spin polarized current that varies in accordance with a relationship between a first magnetization state of said first ferromagnetic layer and a second magnetization state of said second ferromagnetic layer.
24. The spin polarized electron current device of claim 23 , further including a spin polarization enhancement layer situated between said first ferromagnetic layer and said high electrical impedance region adapted to increase a polarization efficiency for transporting said spin polarized current.
25. The spin polarized electron current device of claim 23 , further including a semiconductor gate for controlling conduction in said high electrical impedance region.
26. The spin polarized electron current device of claim 23 , wherein said high electrical impedance region isolates data stored in the device from other data values in a memory array without using a separate isolation element.
27. The spin polarized electron current device of claim 23 wherein at least one of said first ferromagnetic layer and said second ferromagnetic layer have a crescent shaped edge connecting a straight edge.
28. The spin polarized electron current device of claim 23 , wherein a data value is stored in the device in the form of a variable magnetic resistance to said spin polarized current.
29. The spin polarized electron current device of claim 23 , wherein the spin polarized electron current device is part of a read head.
30. The spin polarized electron current device of claim 23 , further including a complementary metal oxide semiconductor (CMOS) sense amplifer coupled to an output of said spin polarized electron current device.
31. The spin polarized electron current device of claim 23 , wherein the spin polarized electron current device is situated on a first level, and at least one second spin polarized electronic current device is stacked over said spin polarized electron current device on a second level.
32. A spin polarized electron current device comprising:
a first ferromagnetic layer having a first coercivity;
a second ferromagnetic layer having a second coercivity larger than said first coercivity;
wherein at least one of said first ferromagnetic layer and said second ferromagnetic layer include an iron-cobalt alloy adapted to inject a spin polarized current into a high electrical impedance region situated between said first ferromagnetic layer and said second ferromagnetic layer;
wherein the spin polarized electron current device is situated on a silicon substrate, and conducts a spin polarized current that varies in accordance with a relationship between a first magnetization state of said first ferromagnetic layer and a second magnetization state of said second ferromagnetic layer.
33. The spin polarized electron current device of claim 32 , further including a spin polarization enhancement layer situated between said first ferromagnetic layer and said high electrical impedance region adapted to increase a polarization efficiency for transporting said spin polarized current.
34. The spin polarized electron current device of claim 32 , further including a semiconductor gate for controlling conduction in said high electrical impedance region.
35. The spin polarized electron current device of claim 32 , wherein said high electrical impedance region isolates data stored in the device from other data values in a memory array without using a separate isolation element.
36. The spin polarized electron current device of claim 32 , wherein at least one of said first ferromagnetic layer and said second ferromagnetic layer have a crescent shaped edge connecting a straight edge.
37. The spin polarized electron current device of claim 32 , wherein a data value is stored in the device in the form of a variable magnetic resistance to said spin polarized current.
38. The spin polarized electron current device of claim 32 , wherein the spin polarized electron current device is part of a read head.
39. The spin polarized electron current device of claim 32 , further including a complementary metal oxide semiconductor (CMOS) sense amplifier coupled to an output of said spin polarized electron current device.
40. The spin polarized electron current device of claim 32 , wherein the spin polarized electron current device is situated on a first level, and at least one second spin polarized electronic current device is stacked over said spin polarized electron current device on a second level.