Magnetic spin based memory with semiconductor selector

1. A hybrid magnetoelectronic spin-based memory cell comprising:

a memory element configured to transport a current of spin polarized electrons including:

i) a first ferromagnetic layer with a first magnetization state;

ii) a second ferromagnetic layer with a second magnetization state;

wherein a magnitude of said current of spin polarized electrons varies in accordance with a relationship between said first magnetization state and said second magnetization state and corresponds to a data value stored in the hybrid magnetoelectronic spin-based memory cell;

a memory element selector coupled to said electron spin-based memory element to isolate said data value, said memory element selector including a semiconductor based transistor which is situated on a silicon based substrate and responds to a read signal for determining said data value.

2. The hybrid magnetoelectronic spin-based memory cell of claim 1 , wherein said memory element is situated above said semiconductor based transistor and is separated by an insulation layer.

3. The hybrid magnetoelectronic spin-based memory cell of claim 1 , wherein an impedance of the memory element is on the order of 1 ohm.

4. The hybrid magnetoelectronic spin-based memory cell of claim 1 wherein a spin transimpedance increases as said memory element decreases in size.

5. The hybrid magnetoelectronic spin-based memory cell of claim 1 further including a low transmission barrier located between said first ferromagnetic layer and said second ferromagnetic layer.

6. The hybrid magnetoelectronic spin-based memory cell of claim 1 , wherein said memory cell selector is coupled to a bit line, and further including a second semiconductor based transistor isolation element coupling said electron spin-based memory element to a bit reference line.

7. The hybrid magnetoelectronic spin-based memory cell of claim 1 wherein the semiconductor based transistor isolation element is a field effect transistor (FET).

8. The hybrid magnetoelectronic spin-based memory cell of claim 1 wherein the semiconductor based transistor isolation element is a bipolar junction transistor (BJT).

9. The hybrid magnetoelectronic spin-based memory cell of claim 1 , further including a read line coupled to read data from said memory element, and a separate write line coupled to write data to said memory element.

10. The hybrid magnetoelectronic spin-based memory cell of claim 9 , wherein said write line uses a single polarity current pulse.

11. The hybrid magnetoelectronic spin-based memory cell of claim 1 , wherein said write line includes two partially overlapping write lines.

12. The hybrid magnetoelectronic spin-based memory cell of claim 11 , wherein said memory element only changes state when a current pulse is present on both of said two overlapping write lines.

13. The hybrid magnetoelectronic spin-based memory cell of claim 1 , wherein said memory element is a spin transistor.

14. The hybrid magnetoelectronic spin-based memory cell of claim 1 , wherein said first ferromagnetic layer and said second ferromagnetic layer each include at least two separate layers.

15. The hybrid magnetoelectronic spin-based memory cell of claim 1 , wherein both a current pulse and a voltage pulse are used to read data stored by said electron spin-based memory element.

16. A hybrid magnetoelectronic spin-based memory cell comprising:

a memory element situated over a silicon based substrate and which is configured to transport a current of spin polarized electrons, including:

i) a first ferromagnetic layer with a first changeable magnetization state comprising iron, permalloy and/or cobalt;

ii) a second ferromagnetic layer with a second non-changeable magnetization state also comprising iron, permalloy and/or cobalt and which conducts said spin current;

wherein a magnitude of a spin polarized current passing through both said first ferromagnetic layer a second ferromagnetic layer can be varied to store a data value in said memory cell having at least two logic levels;

a memory cell selector coupled to said electron spin-based memory, said memory cell selector including a semiconductor based isolation element which can be activated to read said data value.

17. The hybrid magnetoelectronic spin-based memory cell of claim 16 , wherein said memory element is stacked on top of a second electron spin-based memory element.

18. The hybrid magnetoelectronic spin-based memory cell of claim 17 , wherein said memory element and said second electron spin-based memory element share said memory cell selector.

19. The hybrid magnetoelectronic spin-based memory cell of claim 16 , wherein said memory element is a three terminal, current biased device.

20. The hybrid magnetoelectronic spin-based memory cell of claim 16 , including a conductive paramagnetic base layer situated between said first ferromagnetic layer and said second ferromagnetic layer, and which is adapted to create a nonequilibrium population of spin polarized electrons and an equivalent nonequilibrium magnetization M.

21. The hybrid magnetoelectronic spin-based memory cell of claim 20 , wherein said nonequilibrium magnetization M in said paramagnetic conductive paramagnetic base layer base generates an electric field at an interface with said first ferromagnetic layer.

22. The hybrid magnetoelectronic spin-based memory cell of claim 16 , wherein said spin polarized current has a magnitude that varies based on whether said first changeable magnetization state and said second non-changeable magnetization state are parallel or antiparallel.

23. A hybrid magnetoelectronic spin-based memory cell comprising:

a memory element situated over a silicon based substrate and which is configured to transport a current of spin polarized electrons, including:

i) a first ferromagnetic layer with a changeable magnetization state comprising iron, permalloy and/or cobalt;

ii) a second ferromagnetic layer with a non-changeable magnetization state also comprising iron, permalloy and/or cobalt;

iii) a low transmission barrier interface between said first ferromagnetic layer and said second ferromagnetic layer;

wherein said current of spin polarized electrons has a magnitude which can be varied so that a data value can be stored in the memory element by varying a relative orientation of said changeable magnetization state and said non-changeable magnetization state;

a memory cell selector coupled to said memory element, said memory cell selector including a semiconductor based isolation element which is activated to determine said data value by comparing an output voltage of said memory element with a reference voltage.

24. The hybrid magnetoelectronic spin-based memory cell of claim 23 , wherein said output voltage is provided at a terminal coupled to said first ferromagnetic layer.

25. The hybrid magnetoelectronic spin-based memory cell of claim 23 wherein said second ferromagnetic layer is a bilayer including both a first ferromagnetic conductor layer and a second nonmagnetic conductor layer, which second nonmagnetic conductor layer is used to control a magnetic behavior of said first ferromagnetic conductor layer.

26. The hybrid magnetoelectronic spin-based memory cell of claim 23 , further including a read line coupled to read data from said memory element, and a separate write line coupled to write data to said memory element.

27. The hybrid magnetoelectronic spin-based memory cell of claim 23 , wherein said low transmission barrier interface includes Niobium.