Prevention of contamination on bonding pads of wafer during SMT
A semiconductor device is disclosed for preventing contamination on its bonding pads during mounting an electronic component, such as surface mount device (SMD). The semiconductor device includes a semiconductor substrate, a plurality of jointing material and at least an electronic component. A plurality of first bonding pads for wire-bonding and a plurality of second bonding pads for mounting the electronic component are formed on the active surface of the substrate. The substrate includes at least a dam is formed on the active surface to separate the first bonding pads from the second bonding pads. Preferably, the dam surrounds the second bonding pads. The jointing material is disposed on the second bonding pads for bonding the electronic component. Using the dam, there is no flux or tin-lead solder flowing onto the first bonding pads during reflowing the jointing material. In an embodiment, the electronic component can be mounted on the substrate in a wafer level.
1. A semiconductor device comprising:
a) a semiconductor chip having:
i) an active surface having a peripheral region and a central region;
ii) a plurality of first bonding pads formed on the peripheral region of the active surface;
iii) a plurality of second bonding pads formed on the central region of the active surface; and
iv) a patterned passivation layer located on the active surface;
v) at least one dam located on the patterned passivation layer between the plurality of first bonding pads and the plurality of second bonding pads, the at least one dam completely surrounding the plurality of second bonding pads;
b) a jointing material located on the second bonding pads;
c) at least one SMD type passive component mounted on the active surface of the semiconductor chip and having a plurality of electrodes connected to the second bonding pads via the jointing material;
d) a carrier connected to a back surface of the semiconductor chip;
e) a plurality of bonding wires connecting the plurality of first bonding pads to the carrier; and
f) an encapsulant sealing the SMD type passive component and the bonding wires and covering the at least one dam and the active surface of the semiconductor chip.
2. The semiconductor device according to claim 1 , wherein the dam is a rectangular ring.
3. The semiconductor device according to claim 1 , wherein the dam includes a space.
4. The semiconductor device according to claim 3 , wherein the dam is made of a patterned photoresist layer located on the patterned passivation surface to form space.
5. The semiconductor device according to claim 1 , further comprising a under bump metallurgy layer located above the plurality of second bonding pads.
6. The semiconductor device according to claim 1 , wherein the jointing material is tin-lead solder.
7. The semiconductor device according to claim 1 , wherein the jointing material includes flux.
8. The semiconductor device according to claim 1 , wherein the SMD type passive component is selected from a group consisting of a capacitor, a resistor, and an inductor.
9. A method for manufacturing a semiconductor device, which comprises the steps of:
a) providing a semiconductor chip having:
i) an active surface having a peripheral region and a central region;
ii) a plurality of first bonding pads formed on the peripheral region of the active surface;
iii) a plurality of second bonding pads formed on the central region of the active surface;
iv) a patterned passivation layer located on the active surface; and
v) at least one dam located on the patterned passivation layer between the plurality of first bonding pads and the plurality of second bonding pads, the at least one dam completely surrounding the plurality of second bonding pads;
b) applying a jointing material on the second bonding pads;
c) connecting a plurality of electrodes of at least one SMD type passive component to the s second bonding pads located on the active surface of the semiconductor chip via the jointing material;
d) adjoining a carrier to a back surface of the semiconductor chip;
e) connecting the plurality of first bonding pads to the carrier utilizing a plurality of bonding wires; and
f) sealing the SMD type passive component and the bonding wires and covering the at least one dam and the active surface of the substrate semiconductor chip utilizing an encapsulant.
10. The method according to claim 9 , wherein the dam is a rectangular ring.
11. A semiconductor device comprising:
a) a semiconductor chip having:
I) an active surface having a peripheral region and a central region;
ii) a plurality of first bonding pads formed on the peripheral region of the active surface;
iii) a plurality of second bonding pads formed on the central region of the active surface;
iv) a patterned passivation layer located on the active surface and having at least one dam located between the plurality of first bonding pads and the plurality of second bonding pads and at least one space located between the at least one dam and the plurality of second bonding pads, the at least one dam completely surrounding the plurality of second bonding pads wherein the space and the dam are integrally formed by the patterned passivation layer, and the space is configured for preventing the jointing material from contaminating the first bonding pads; and
b) a jointing material located on the second bonding pads, wherein the space and the dam are integrally formed by the patterned passivation layer, and the space is configured for preventing the jointing material from contaminating the first bonding pads;
c) at least one SMD type passive component mounted on the active surface of the semiconductor chip and having a plurality of electrodes connected to the second bonding pads via the jointing material;
d) a carrier connected to a back surface of the semiconductor chip;
e) a plurality of bonding wires connecting the plurality of first bonding pads to the carrier; and
f) an encapsulant sealing the SMD type passive component and the bonding wires and covering the at least one dam and the active surface of the semiconductor chip.
12. The semiconductor device according to claim 11 , wherein the dam is a rectangular ring.
13. The semiconductor device according to claim 11 , further comprising a space located between the dam and the plurality of first bonding pads.
14. The semiconductor device according to claim 11 , further comprising a under bump metallurgy layer located above the plurality of second bonding pads.
15. The semiconductor device according to claim 11 , wherein the jointing material is tin-lead solder.
16. The semiconductor device according to claim 11 , wherein the jointing material includes flux.
17. The semiconductor device according to claim 11 , wherein the SMD type passive component is selected from a group consisting of a capacitor, a resistor, and an inductor.