Timer circuit with adaptive reference
View Patent ↗A timer circuit includes a current mirror, a capacitor, a first switch, a resistor and a comparator. The current mirror receives a reference current and provides first and second currents with a predefined current ratio. The first switch, controlled by a control signal, allows the capacitor to be charged by the first current or be discharged. The resistor is biased by the second current to provide an adaptive reference voltage. The comparator compares the voltage across the capacitor and the adaptive reference voltage and triggers an output signal when the capacitor voltage is increased to the adaptive reference voltage. Alternately, the timer circuit includes a pin for coupling to an external resistor and an open pin detector circuit to detect the presence of the external resistor and to automatically select the adaptive reference voltage if a resistor is present or an internal reference voltage if the resistor is absent.
1. A timer circuit comprising:
a current mirror receiving a reference current as an input current, the current mirror providing a first output current on a first output node and a second output current on a second output node, the second output current being N times the first output current;
a capacitor coupled between the first output node and a first power supply voltage, the capacitor receiving the first output current when being charged;
a first switch coupled between the first output node and the first power supply voltage, the first switch being controlled by a first control signal to be in a first position for discharging the capacitor to the first power supply voltage and in a second position to allow the capacitor to be charged by the first output current;
a resistor coupled between the second output node and the first power supply voltage, the resistor being biased by the second output current to develop a reference voltage across the resistor; and
a comparator having a first input terminal coupled to the first output node and a second input terminal coupled to the second output node, the comparator providing an output signal having a first state when the voltage across the capacitor at the first output node is less than the reference voltage and providing an output signal having a second state when the voltage across the capacitor is equal to or greater than the reference voltage;
a reference voltage circuit for generating a second reference voltage; and
a second switch coupled to the second input terminal of the comparator and being controlled by a second control signal, the second switch being in a first position for connecting the reference voltage across the resistor to the second input terminal of the comparator and being in a second position for connecting the second reference voltage from the reference voltage circuit to the second input terminal of the comparator,
wherein the comparator receives either the reference voltage or the second reference voltage as a comparison reference voltage, the comparator providing an output signal having a first state when the voltage across the capacitor at the first output node is less than the comparison reference voltage and providing an output signal having a second state when the voltage across the capacitor is equal to or greater than the comparison reference voltage.
2. The timer circuit of claim 1 , wherein the first control signal is deasserted to cause the first switch to be in the first position to discharge the capacitor and the first control signal is asserted to cause the first switch to be in the second position to allow the capacitor to be charged by the first output current, thereby initiating a predetermined time duration.
3. The timer circuit of claim 2 , wherein upon assertion of the first control signal, the voltage across the capacitor increases as the capacitor is being charged by the first output current, the output signal of the comparator is triggered from the first state to the second state when the voltage across the capacitor reaches the reference voltage, the timer circuit providing the predetermined time duration from the assertion of the first control signal to the triggering of the output signal of the comparator.
4. The timer circuit of claim 3 , wherein the time duration is a product of the capacitance of the capacitor, the resistance of the resistor and N.
5. The timer circuit of claim 1 , wherein N is greater than one.
6. The timer circuit of claim 1 , wherein the timer circuit is built on an integrated circuit and the resistor is an integrated resistor built on the same integrated circuit, the integrated resistor having tight tolerance and negligible temperature coefficient.
7. The timer circuit of claim 1 , wherein the timer circuit is built on an integrated circuit and the resistor comprises a discrete resistor external to the integrated circuit and being coupled to the integrated circuit to receive the second output current.
8. The timer circuit of claim 1 , wherein the second control signal is generated by a circuit detecting the presence or absence of the resistor, the second control signal being asserted to cause the second switch to be in the first position when the resistor is present and the second control signal being deasserted to cause the second switch to be in the second position when the resistor is absent.
9. The timer circuit of claim 1 , wherein the first power supply voltage comprises the ground voltage.
10. A timer circuit formed in an integrated circuit, the timer circuit comprising:
a current mirror receiving a reference current as an input current, the current mirror providing a first output current on a first output node and a second output current on a second output node, the second output current being N times the first output current;
a capacitor coupled between the first output node and a first power supply voltage, the capacitor receiving the first output current when being charged;
a first switch coupled between the first output node and the first power supply voltage, the first switch being controlled by a first control signal to be in a first position for discharging the capacitor to the first power supply voltage and in a second position to allow the capacitor to be charged by the first output current;
a pin formed on the integrated circuit and being coupled to the second output node for receiving the second output current, a first reference voltage being developed at the pin when a resistor is coupled to the pin and biased by the second output current;
a reference voltage circuit for generating a second reference voltage;
a second switch coupled to a third node and being controlled by a second control signal, the second switch being in a first position for connecting the first reference voltage at the pin to the third node and being in a second position for connecting the second reference voltage from the reference voltage circuit to the third node;
an open pin detector circuit generating the second control signal, the open pin detector circuit asserting the second control signal to cause the second switch to be in the first position when the pin is coupled to a resistor and the open pin detector circuit deasserting the second control signal to cause the second switch to be in the second position when the pin is an open circuit; and
a comparator having a first input terminal coupled to the first output node and a second input terminal coupled to the third node, the third node receiving either the first or second reference voltage as a comparison reference voltage, the comparator providing an output signal having a first state when the voltage across the capacitor at the first output node is less than the comparison reference voltage and providing an output signal having a second state when the voltage across the capacitor is equal to or greater than the comparison reference voltage.
11. The timer circuit of claim 10 , wherein the first control signal is deasserted to cause the first switch to be in the first position to discharge the capacitor and the first control signal is asserted to cause the first switch to be in the second position to allow the capacitor to be charged by the first output current, thereby initiating a predetermined time duration.
12. The timer circuit of claim 11 , wherein upon assertion of the first control signal, the voltage across the capacitor increases as the capacitor is being charged by the first output current, the output signal of the comparator is triggered from the first state to the second state when the voltage across the capacitor reaches the reference voltage, the timer circuit providing the predetermined time duration from the assertion of the first control signal to the triggering of the output signal of the comparator.
13. The timer circuit of claim 10 , wherein N is greater than one.
14. The timer circuit of claim 10 , wherein a discrete resistor is coupled to the pin to generate the first reference voltage.
15. The timer circuit of claim 14 , wherein the time duration is a product of the capacitance of the capacitor, the resistance of the resistor and N.
16. The timer circuit of claim 10 , wherein the current mirror further provides a third output current at a third output node, and the reference voltage circuit comprises an integrated resistor having tight tolerance and negligible temperature coefficient, the integrated resistor being biased by the third output current so that a voltage across the integrated resistor comprises the second reference voltage.
17. The timer circuit of claim 10 , wherein the second switch comprises a third switch controlled by a third control signal and a fourth switch controlled by a fourth control signal, and the open pin detector circuit comprise:
a comparator having a first input terminal coupled to receive the first reference voltage and a second input terminal coupled to receive a threshold voltage, the threshold voltage being greater than the first reference voltage when a resistor is coupled to the pin and smaller than the first reference voltage when no resistor is coupled to the pin, the comparator providing a second output signal having a first state when the first reference voltage is smaller than the threshold voltage and a second state when the first reference voltage is greater than the threshold voltage;
an non-inverting buffer having an input terminal coupled to receive the second output signal, the non-inverting buffer providing the third control signal;
an inverting buffer having an input terminal coupled to receive the third control signal, the inverting buffer providing the fourth control signal;
the third switch being coupled between the third node and the pin, the third switch being closed when the third control signal is asserted in response to the second output signal having the first state; and
the fourth switch being coupled between the third node and the reference voltage circuit for receiving the second reference voltage, the fourth switch being closed when the fourth control signal is asserted in response to the second output signal having the second state.
18. A method for providing a time duration from the assertion of a first control signal, the method comprising:
generating a first current and a second current by mirroring a reference current, the second current being N times the first current;
coupling the first current to a capacitor;
coupling the second current to a resistor;
charging the capacitor to a first voltage when the first control signal is deasserted;
charging the voltage across the capacitor using the first current when the first control signal is asserted;
providing a reference voltage;
selecting a comparison reference voltage being either the voltage across the resistor or the reference voltage;
comparing the voltage across the capacitor to the comparison reference voltage; and
triggering an output signal when the voltage across the capacitor is equal to the comparison reference voltage,
wherein the time duration comprises the time between the assertion of the first control signal and the triggering of the output signal.
19. The method of claim 18 , wherein charging the capacitor to a first voltage comprises discharging the capacitor to a first power supply voltage and charging the voltage across the capacitor using the first current comprises charging the capacitor using the first current to increase the voltage across the capacitor.
20. The method of claim 19 , wherein triggering an output signal comprises transitioning the output signal from a logical low state to a logical high state.
21. The method of claim 19 , wherein the first power supply voltage comprises the ground voltage.
22. The method of claim 18 , wherein charging the capacitor to a first voltage comprises charging the capacitor to a second power supply voltage and charging the voltage across the capacitor using the first current comprises discharging the capacitor using the first current to decrease the voltage across the capacitor.
23. The method of claim 22 , wherein triggering an output signal comprises transitioning the output signal from a logical high state to a logical low state.
24. The method of claim 22 , wherein the second power supply voltage comprises a positive power supply voltage.
25. The method of claim 18 , wherein N is greater than one.