IP Library Granted Patent US 7,176,580
Granted Patent B1
US 7,176,580 · App. 10/973,172 · Granted Feb 13, 2007

Structures and methods for wire bonding over active, brittle and low K dielectric areas of an IC chip

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Quick Facts
Patent No.
US 7,176,580
App. No.
10/973,172
Granted
Feb 13, 2007
Kind
B1
Abstract

Disclosed are structures and methods that facilitate the use of wire bonding technology over active areas of an IC chip. The invention is also suitable for use with IC structures that use brittle dielectric materials such as low K dielectrics.

Claims (16)

1. An integrated circuit chip termination structure suitable for making a wire bond over one or more active brittle surface areas of a chip, wherein the integrated circuit chip termination structure comprises:

a bond pad on a surface of the integrated circuit chip;

a conductive bump disposed on the bond pad; and

a wire having a terminal end bonded to the conductive bump, wherein the conductive bump comprises a size configured to spread a compressive force against the surface of the integrated chip during fabrication over an area sufficient to effectively reduce chip damage during fabrication.

2. The integrated circuit chip termination of claim 1 , where the conductive bump is formed from a metal.

3. The integrated circuit chip termination of claim 1 , where the conductive bump includes a conductive adhesive.

4. The integrated circuit chip termination of claim 2 , where the metal comprises tin.

5. The integrated circuit chip termination of claim 2 , where the metal comprises a solder alloy.

6. The integrated circuit chip termination of claim 2 , where metal comprises copper.

7. The integrated circuit chip termination of claim 2 , where metal comprises nickel.

8. The integrated circuit chip termination of claim 7 , where the nickel metal is plated with a wire bondable metal.

9. The integrated circuit chip termination of claim 8 , where the metal is from the group of noble metals on the periodic chart of elements that includes gold.

10. The integrated circuit chip termination of claim 1 , where the chip termination structure comprises transient liquid phase bonding elements.

11. The integrated circuit chip termination of claim 1 , where the chip termination structure comprises solder.

12. The integrated circuit chip termination of claim 1 , where the chip termination structure comprises adhesive bonding.

13. The integrated circuit chip termination of claim 1 , where the terminal end of the wire comprises a coined ball having micro asperities configured to increase a bond strength.

Assignments (7)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2010
From: TECHNOLOGY PROPERTIES LIMITED
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 025105/0596 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 7, 2010
From: INTERCONNECT PORTFOLIO, LLC; INTELLASYS BEC LIMITED; TECHNOLOGY PROPERTIES LIMITED
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 025105/0634 →
LICENSE Recorded Mar 4, 2009
From: INTERCONNECT PORTFOLIO LLC
To: TECHNOLOGY PROPERTIES LIMITED LLC
Reel/Frame 022343/0351 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 18, 2008
From: NOVIAS LLC
To: INTERCONNECT PORTFOLIO, LLC
Reel/Frame 021861/0127 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 24, 2008
From: HOLDERS, SECURE NOTE; ANDERSON, DAN; FJELSTAD, JOE; GRUNDY, KEVIN; GRUNDY, LAWRENCE; STEPOVICH, MATT
To: NOVIAS, LLC
Reel/Frame 021744/0512 →
FORECLOSURE BY SECURE NOTE HOLDERS Recorded Aug 7, 2008
From: SILICON PIPE, INC.
To: SECURE NOTE HOLDERS: DAN ANDERSON, JOSEPH FJELSTAD, KEVIN GRUNDY, LAURANCE GRUNDY, MATT STEPOVICH
Reel/Frame 021380/0276 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 25, 2004
From: FJELSTAD, JOSEPH
To: SILICONPIPE, INC
Reel/Frame 015934/0574 →