Scan test method, integrated circuit, and scan test circuit
View Patent ↗A scan test method of an integrated circuit including a combinational circuit and flip-flops forming a scan chain is disclosed. The method first sets an initial test value to the flip-flops forming the scan chain by serial scan input. Then, it repeats a capture operation and a feedback shift operation. The capture operation captures an output of the combinational circuit, to which a value set to a flip-flop has been applied, by another flip-flop. The feedback shift operation feeds an output of the scan chain back to an input side of the scan chain for re-input during a shift operation in the scan chain. Finally, it compares an output of the scan chain with an expected value.
1. A scan test method of an integrated circuit including a combinational circuit, there being a flip-flop coupled to an input of the combination circuit and a flip-flop coupled to an output of the combination circuit, said flip-flops forming a scan chain, comprising:
setting initial test values to the flip-flops forming the scan chain;
performing a first capture operation whereby a first output of the combination circuit is captured by said flip-flop coupled to the output of the combination circuit;
performing a feedback shift operation feeding said first output of the scan chain back to an input side of the scan chain for re-input during a shift operation in the scan chain;
performing a second capture operation, whereby a second output of the combination circuit based on inputting said first output to said combination circuit is captured by said flip-flop coupled to the output of the combination circuit; and
comparing said second output of the scan chain, output after performing the second capture operation, with an expected value.
2. The scan test method according to claim 1 , wherein each of the capture operation and the feedback shift operation are performed alternately for a predetermined number of times.
3. The scan test method according to claim 2 , wherein, if the number of flip-flops forming the scan chain is N where N is a positive integer of 2 or greater, the number of times to perform the shift operation in each feedback shift operation is 1 or greater, and not a multiple of N.
4. The scan test method according to claim 3 , wherein the number of times to perform the shift operation in each feedback shift operation is within a range of 1 to (N−1).
5. The scan test method according to claim 4 , wherein another initial test value is set to the flip-flops forming the scan chain during performing of each of the capture operation and the feedback shift operation.
6. The scan test method according to claim 3 , wherein another initial test value is set to the flip-flops forming the scan chain during performing of each of the capture operation and the feedback shift operation.
7. The scan test method according to claim 2 , wherein another initial test value is set to the flip-flops forming the scan chain during performing of each of the capture operation and the feedback shift operation.
8. The scan test method according to claim 1 , wherein, if the number of flip-flops forming the scan chain is N where N is a positive integer of 2 or greater, the number of times to perform the shift operation in each feedback shift operation is set to 1 or greater, and not a multiple of N.
9. The scan test method according to claim 8 , wherein the number of times to perform the shift operation in each feedback shift operation is within a range of 1 to (N−1).
10. The scan test method according to claim 9 , wherein another initial test value is set to the flip-flops forming the scan chain during performing of each of the capture operation and the feedback shift operation.
11. The scan test method according to claim 8 , wherein another initial test value is set to the flip-flops forming the scan chain during performing of each of the capture operation and the feedback shift operation.
12. A scan test method of an integrated circuit including a combinational circuit, there being a flip-flop coupled to an input of the combination circuit and a flip-flop coupled to an output of the combination circuit, said flip-flops forming a scan chain, comprising:
setting initial test values to the flip-flops forming the scan chain;
performing a first capture operation whereby an output of the combination circuit is captured by said flip-flop coupled to the output of the combination circuit;
performing a feedback shift operation feeding an output of the scan chain back to an input side of the scan chain for re-input during a shift operation in the scan chain;
performing a second capture operation, after the feedback shift operation, whereby an output of the combination circuit is captured by said flip-flop coupled to the output of the combination circuit;
performing a capture repeat operation comprising performing the feedback shift operation and the second capture operation at least once; and
comparing an output of the scan chain, output after performing the capture repeat operation, with an expected value.
13. The scan test method according to claim 1 , further comprising outputting all the values stored in the flip-flops forming the scan chain.
14. The scan test method according to claim 1 , wherein no additional test patterns are read into the scan chain from the input side of the scan chain.