Granted Patent B2

US 7,402,868 · App. 10/976,816 · Granted Jul 22, 2008

Abstract

Claims (34)

1. A semiconductor memory comprising:

a plurality of charge trapping layers;

a plurality of word lines, where each charge trapping layer is electrically insulated from a word line of the plurality of word lines;

a capacitor;

a first structure connected to the capacitor; and

a plurality of second structures, each of the second structures being associated with a different word line of the plurality of word lines and being configured to connect the associated word line to the first structure.

2. The semiconductor memory device of claim 1 wherein the first structure is configured to leak current from the plurality of word lines to the capacitor.

3. The semiconductor memory device of claim 1 wherein a length of each of the plurality of second structures ranges from about 1 μm to 5 μm.

4. The semiconductor memory device of claim 1 wherein each of the second structures comprises a silicided portion and an unsilicided portion.

5. The semiconductor memory device of claim 4 wherein the first structure comprises a silicided portion and an unsilicided portion, and

wherein the unsilicided portion of each second structure is located adjacent to the unsilicided portion of the first structure.

6. The semiconductor memory device of claim 1 wherein the first structure connects to a substrate of the semiconductor memory device via a metal-1 tap.

7. A semiconductor memory device comprising:

a vertical stack including a charge trapping layer electrically insulated from one word line of a plurality of word lines; and

a structure configured to dissipate current from the plurality of word lines during fabrication of the semiconductor memory device, the structure comprising:

a thin-oxide capacitor,

a polysilicon strap connected to the thin-oxide capacitor, and

a plurality of polysilicon extensions, each polysilicon extension being connected to a different word line of the plurality of word lines and connecting the word line to the polysilicon strap.

8. The semiconductor memory device of claim 7 wherein the polysilicon strap connects to a substrate of the semiconductor memory device via a metal-1 tap.

9. A memory cell comprising:

a vertical stack including a charge trapping layer electrically insulated from a word line disposed on the stack;

a capacitor electrically coupled to the word line;

a first structure to connect the word line to the capacitor and leak current from the word line to the capacitor; and

a metal-1 tap configured to connect the first structure to a substrate and leak current to the substrate.

10. The memory cell of claim 9 wherein the charge trapping layer is formed from one of a silicon nitride material, a silicon oxide material, or another dielectric material.

11. The memory cell of claim 9 wherein the word line, the capacitor, and the first structure are formed of a same material.

12. The memory cell of claim 11 wherein the same material comprises polysilicon.

13. The memory cell of claim 9 wherein the word line is associated with an extension that connects the word line to the first structure.

14. The memory cell of claim 13 wherein a length of the extension ranges from about 1 μm to about 5 μm.

15. The memory cell of claim 13 wherein the extension comprises a silicided portion and an unsilicided portion.

16. The memory cell of claim 15 wherein a length of the unsilicided portion of the extension ranges from about 1 μm to about 2 μm.

17. The memory cell of claim 15 wherein the first structure comprises a silicided portion and an unsilicided portion, and wherein the unsilicided portion of the extension is located adjacent to the unsilicided portion of the first structure.

18. The memory cell of claim 9 wherein a height of each of the word line, the capacitor, and the first structure ranges from about 500 Å to about 3000 Å.

19. The memory cell of claim 9 wherein the first structure is configured to leak current from the word line to the capacitor during process charging.

Assignments (9)