Single data line sensing scheme for TCCT-based memory cells
View Patent ↗A sensing circuit including a sense amplifier to resolve a data signal generated by a memory cell is disclosed herein. The sensing circuit includes a bit line to receive the data signal, a first pre-charge device coupled to the bit line and configured to pre-charge the bit line, a device for providing a bias coupled to the bit line and configured to provide a bias to the bit line, and a reference node configured to be at least one pre-determined level. In one embodiment the pre-determined level is equal to a low potential such as ground and in another embodiment equal to a high potential such as V DD . One or more switching devices allows for the activation or deactivation of the pre-charge device allowing to pre-charge the bit line to a certain potential and the sensing circuit quickly and accurately determines whether a logical state of ‘1’ or ‘0’ is being applied to the bit line.
1. A method of controlling a sensing circuit, the method comprising:
coupling a bit line to a first node, the first node associated with a first sense amplifier input;
pre-charging the bit line to a pre-determined level;
pre-charging the first node to the pre-determined level;
applying a bias to the bit line;
floating the bit line;
floating the first node; and
transferring a data signal from a TCCT-based memory cell onto the bit line.
2. The method of claim 1 , further comprising resolving the data signal including:
applying the data signal from the bit line to the first node;
decoupling the bit line and the first node; and
determining a logical value in which the data signal represents.
3. The method of claim 1 , further comprising enabling operation of a sense amplifier.
4. The method of claim 1 , wherein the coupling of the bit line to the first node is during non-resolving operation of the sense amplifier.
5. The method of claim 1 , the method further comprising:
coupling a reference node at the pre-determined level to a second node, the second node associated with a second sense amplifier input;
floating the reference node; and
floating the second node.
6. The method of claim 5 , wherein the coupling the reference bit line to the second node is during non-resolving operation of the sense amplifier.
7. The method of claim 5 , wherein the reference memory cell includes a TCCT device.
8. The method of claim 5 , further comprising using the reference signal including:
applying the reference node to the second node; and
decoupling the reference node and the second node.
9. The method of claim 5 , wherein the pre-determined level is ground.
10. The method of claim 5 , wherein the pre-determined level is substantially the same as a power supply potential.