Clock scaling circuit
View Patent ↗Techniques for scaling and switching clocks in a glitch-free manner are provided. For example, in one aspect of the present invention, a technique for switching a frequency associated with a master clock includes the following steps/operations. Two phase clocks are generated from a master clock, wherein the two phase clocks do not transition at substantially the same time. Then, one of the two phase clocks is used to create multiple frequencies by dividing the one phase clock, and the other phase clock is used to switch between the multiple frequencies of the one phase clock. Further, one of the two phase clocks may be in phase with the master clock and the other of the two phase clocks may be 180 degrees out of phase with the master clock such that they do not transition at the same time. Also, the two phase clocks may be non-overlapping.
1. A method of switching a frequency associated with a master clock, comprising the steps of:
generating two phase clocks from a master clock, wherein the two phase clocks do not transition at substantially the same time;
using one of the two phase clocks to create multiple frequencies by dividing the one phase clock; and
using the other phase clock to switch between the multiple frequencies of the one phase clock.
2. The method of claim 1 , further comprising the step of selecting one of the multiple frequencies of the one phase clock, such that the frequency associated with the master clock is switched to the selected frequency.
3. The method of claim 2 , wherein the selecting step is programmable.
4. The method of claim 2 , further comprising the step of outputting a new master clock signal at the selected frequency.
5. The method of claim 1 , wherein one of the two phase clocks is in phase with the master clock and the other of the two phase clocks is 180 degrees out of phase with the master clock.
6. The method of claim 1 , wherein the two phase clocks are non-overlapping.
7. The method of claim 1 , wherein the master clock is switched from one clock frequency to a new clock frequency within half the period of the new clock frequency.
8. The method of claim 1 , wherein the frequency of the master clock is switched in order to detect at least one dynamic fault.
9. The method of claim 8 , wherein circuits are sorted as a function of operating frequency based upon dynamic fault detection.
10. Apparatus for switching a frequency associated with a master clock, comprising:
a clock splitter for generating two phase clocks from a master clock, wherein the two phase clocks do not transition at substantially the same time;
multiple clock dividers for creating multiple frequencies by dividing one of the two phase clocks; and
means for switching between the multiple frequencies of the one of the two phase clocks using the other of the two phase clocks.
11. The apparatus of claim 10 , wherein the switching means comprises a finite state machine and a multiplexer.
12. Apparatus for switching a frequency associated with a master clock, comprising:
a memory; and
at least one processor coupled to the memory and operative to: (i) generate two phase clocks from a master clock, wherein the two phase clocks do not transition at substantially the same time; (ii) use one of the two phase clocks to create multiple frequencies by dividing the one phase clock; and (iii) use the other phase clock to switch between the multiple frequencies of the one phase clock.
13. The apparatus of claim 12 , wherein the at least one processor is further operative to select one of the multiple frequencies of the one phase clock, such that the frequency associated with the master clock is switched to the selected frequency.
14. The apparatus of claim 13 , wherein the selecting operation is programmable.
15. The apparatus of claim 13 , wherein the at least one processor is further operative to output a new master clock signal at the selected frequency.
16. The apparatus of claim 12 , wherein one of the two phase clocks is in phase with the master clock and the other of the two phase clocks is 180 degrees out of phase with the master clock.
17. The apparatus of claim 12 , wherein the two phase clocks are non-overlapping.
18. The apparatus of claim 12 , wherein the master clock is switched from one clock frequency to a new clock frequency within half the period of the new clock frequency.
19. The apparatus of claim 12 , wherein the frequency of the master clock is switched in order to detect at least one dynamic fault.
20. The apparatus of claim 19 , wherein circuits are sorted as a function of operating frequency based upon dynamic fault detection.
21. An article of manufacture for switching a frequency associated with a master clock, comprising a machine readable medium containing one or more programs which when executed implement the steps of:
generating two phase clocks from a master clock, wherein the two phase clocks do not transition at substantially the same time;
using one of the two phase clocks to create multiple frequencies by dividing the one phase clock; and
using the other phase clock to switch between the multiple frequencies of the one phase clock.