Compensation for test signal degradation due to DUT fault
View Patent ↗An electronic device tester channel transmits a single test signal to multiple terminals of electronic devices under test (DUTs) through a set of isolation resistors. The tester channel employs feedback to automatically adjust the test signal voltage to compensate for affects of faults at any of the DUT terminals to prevent the faults from substantially affecting the test signal voltage.
1. A method for concurrently transmitting a test signal to a plurality of integrated circuit (IC) terminals of ICs during a test of the ICs, wherein a voltage of the test signal repeatedly transitions between first and second test signal voltage levels representing first and second logic levels when a control signal repeatedly transitions between first and second states, wherein at least one fault linking at least one of the plurality of IC terminals to a source of potential has no substantial effect on the first and second logic levels represented by the test signal at others of the IC terminals, the method comprising the steps of:
a. driving an output signal between first and second output signal voltage levels when the control signal transitions between the first and second states,
b. resistively coupling the output signal to a circuit node to produce the test signal at the circuit node,
c. concurrently distributing the test signal from the circuit node to the plurality of IC terminals though paths resistively isolating the IC terminals from one another, and
d. adjusting the first and second output signal voltage levels such that the test signal transitions between the first and second test signal voltage levels when the control signal transitions between said first and second states.
2. The method in accordance with claim 1 wherein the first and second test signal voltage levels are adjusted at step d during the test.
3. The method in accordance with claim 1 wherein the first and second test signal voltage levels are adjusted at step d prior to the test and held constant during the test.
4. The method in accordance with claim 3 wherein the second output signal voltage level is more positive than the first output signal voltage level, and wherein step a comprises the substeps of:
a1. responding to a change in the control signal from the first state to the second state, by initially driving the output signal voltage substantially more positive than the second output signal voltage level, and thereafter driving the output signal voltage to the second output signal voltage, and
a2. responding to a change in the control signal from the second state to the first state, by initially driving the output signal voltage substantially more negative than the first output signal voltage level, and thereafter driving the output signal voltage to the first output signal voltage.
5. The method in accordance with claim 1 wherein step d comprises the substeps of:
d1. performing a first comparison between the test signal voltage and a first reference voltage when the control signal is of the first state
d2. adjusting first data in response to the first comparison,
d3. performing a second comparison between the test signal voltage and a second reference voltage when the control signal is of the second state,
d4. adjusting second data in response to the second comparison,
d5. storing the first and second data adjusted at steps d1 and d3, and
d6. controlling the first and second output signal voltage levels in response to the stored first and second data.
6. The method in accordance with claim 5
wherein step d5 occurs prior to the test, and
wherein the first and second output signal voltage levels remain constant during the test.
7. The method in accordance with claim 1 wherein step d comprises the substeps of:
d1. during the test, performing a first comparison between the test signal voltage and a first reference voltage and adjusting the first output signal voltage level in accordance with the first comparison when the control signal is of the first state, and
d2. during the test, performing a second comparison between the test signal voltage and a second reference voltage and adjusting the second output signal voltage level in accordance with the second comparison when the control signal is of the second state.
8. The method in accordance with claim 1 wherein step d comprises the substeps of:
d1. prior to the test, performing a first comparison between the test signal voltage and a first reference voltage when the control signal is of the first state;
d2. prior to the test, adjusting the first output signal voltage level in accordance with the first comparison;
d3. prior to the test, performing a second comparison between the test signal voltage and a second reference voltage when the control signal is of the second state;
d4. prior to the test, adjusting the second output signal voltage level in accordance with the second comparison; and
d5. during the test, the refraining from further adjusting the first and second output signal voltage levels.