Memory device and method for simultaneously programming and/or reading memory cells on different levels
View Patent ↗A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.
1. A memory device comprising:
a three-dimensional memory array comprising:
a first level of memory cells;
a second level of memory cells; and
a plurality of conductor layers comprising first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers; and
circuitry operative to simultaneously program at least two memory cells, at least one in the first level and at least one in the second level.
2. The memory device of claim 1 , wherein the first level of memory cells and the second level of memory cells are built over a silicon substrate.
3. The memory device of claim 1 , wherein the memory cells in the first and second levels comprise write-once memory cells.
4. The memory device of claim 1 , wherein the memory cells in the first and second levels comprise write-many memory cells.
5. The memory device of claim 1 further comprising:
circuitry operative to simultaneously read at least two memory cells, at least one in the first level and at least one in the second level.
6. A memory device comprising:
a first level of memory cells;
a second level of memory cells;
circuitry operative to simultaneously program at least two memory cells, at least one in the first level and at least one in the second level; and
a plurality of conductor layers, wherein the first and second levels of memory cells are between the plurality of conductor layers;
wherein the plurality of conductor layers comprises first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layer; and
wherein the first, second, and third conductor layers each comprise a respective plurality of conductor lines, and wherein the conductor lines of the first conductor layer are perpendicular to the conductor lines of the second conductor layer, and wherein the conductor lines of the second conductor layer are perpendicular to the conductor lines of the third conductor layer.
7. A memory device comprising:
a three-dimensional memory array comprising:
a first level of memory cells;
a second level of memory cells; and
a plurality of conductor layers comprising first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers; and
circuitry operative to simultaneously read at least two memory cells, at least one in the first level and at least one in the second level.
8. The memory device of claim 7 , wherein the first level of memory cells and the second level of memory cells are built over a silicon substrate.
9. The memory device of claim 7 , wherein the memory cells in the first and second levels comprise write-once memory cells.
10. The memory device of claim 7 , wherein the memory cells in the first and second levels comprise write-many memory cells.
11. A memory device comprising:
a first level of memory cells;
a second level of memory cells;
circuitry operative to simultaneously read at least two memory cells, at least one in the first level and at least one in the second level; and
a plurality of conductor layers, wherein the first and second levels of memory cells are between the plurality of conductor layers;
wherein the plurality of conductor layers comprises first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers; and
wherein the first, second, and third conductor layers each comprise a respective plurality of conductor lines, and wherein the conductor lines of the first conductor layer are perpendicular to the conductor lines of the second conductor layer, and wherein the conductor lines of the second conductor layer are perpendicular to the conductor lines of the third conductor layer.
12. A method comprising:
with a memory device comprising first and second levels of memory cells and a plurality of conductor layers comprising first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers, performing at least one of the following:
(a) simultaneously programming at least two memory cells, at least one in the first level and at least one in the second level; and
(b) simultaneously reading at least two memory cells, at least one in the first level and at least one in the second level.
13. The method of claim 12 , wherein the first level of memory cells and the second level of memory cells are built over a silicon substrate.
14. The method of claim 12 , wherein the memory cells in the first and second levels comprise write-once memory cells.
15. The method of claim 12 , wherein the memory cells in the first and second levels comprise write-many memory cells.
16. A method comprising:
(a) providing a memory device comprising first and second levels of memory cells; and
(b) performing at least one of the following:
(b1) simultaneously programming at least two memory cells, at least one in the first level and at least one in the second level; and
(b2) simultaneously reading at least two memory cells, at least one in the first level and at least one in the second level;
wherein the memory device further comprises a plurality of conductor layers, wherein the first and second levels of memory cells are between the plurality of conductor layers;
wherein the plurality of conductor layers comprises first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers; and
wherein the first, second, and third conductor layers each comprise a respective plurality of conductor lines, and wherein the conductor lines of the first conductor layer are perpendicular to the conductor lines of the second conductor layer, and wherein the conductor lines of the second conductor layer are perpendicular to the conductor lines of the third conductor layer.
17. A memory device comprising:
a first level of memory cells;
a second level of memory cells;
a plurality of conductor layers comprising first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers;
circuitry operative to simultaneously read at least two memory cells, at least one in the first level and at least one in the second level; and
a plurality of sense amplifiers, one sense amplifier for each of the at least two memory cells.
18. A method comprising:
with a memory device comprising first and second levels of memory cells and a plurality of conductor layers comprising first, second, and third conductor layers, wherein the first level of memory cells is between the first and second conductor layers, and wherein the second level of memory cells is between the second and third conductor layers, performing at least one of the following:
(a) simultaneously programming at least two memory cells, at least one in the first level and at least one in the second level; and
(b) simultaneously reading at least two memory cells, at least one in the first level and at least one in the second level;
wherein the at least two memory cells are simultaneously read in (b) using a plurality of sense amplifiers, one sense amplifier for each of the at least two memory cells.