Process for fabricating an integrated circuit package with reduced mold warping
View Patent ↗A process for fabricating an integrated circuit package includes mounting a semiconductor die on a first surface of a metal carrier and forming electrical connections between the semiconductor die and ones of a plurality of contacts on the metal carrier. Next, using a molding material in a mold, the semiconductor die and the contacts are molded in the molding material, between the metal carrier and a metal strip. The metal carrier and the metal strip are etched away and the integrated circuit package is singulated.
1. A process for fabricating an integrated circuit package, comprising:
mounting a semiconductor die on a first surface of a metal carrier and forming electrical connections between said semiconductor die and ones of a plurality of contacts on said metal carrier;
molding using a molding material in a mold to thereby mold the semiconductor die and the contacts in the molding material, between said metal carrier and a metal strip;
etching away said metal carrier and said metal strip; and singulating said integrated circuit package.
2. The process for fabricating the integrated circuit package according to claim 1 , further comprising:
placing one of said metal carrier and said metal strip in a mold cavity in the mold; and
releasably clamping the other of said metal carrier and said metal strip to a die of said mold, prior to molding in said molding material.
3. The process for fabricating an integrated circuit package according to claim 1 , wherein said semiconductor die is mounted to a die attach pad on said first surface of said metal carrier.
4. The process for fabricating the integrated circuit package according to claim 3 , wherein said mounting said semiconductor die further comprises wire bonding said semiconductor die to ones of the contacts.
5. The process for fabricating the integrated circuit package according to claim 1 , wherein said semiconductor die is directly mounted to said first surface of said metal carrier.
6. The process for fabricating the integrated circuit package according to claim 5 , wherein said mounting said semiconductor die further comprises wire bonding said semiconductor die to ones of the contacts.
7. The process for fabricating the integrated circuit package according to claim 1 , wherein mounting said semiconductor die comprises flip-chip mounting said semiconductor die to said plurality of contacts to thereby form said electrical connections.
8. The process for fabricating the integrated circuit package according to claim 1 , first comprising selectively plating at least one layer of metal on said first surface of said metal carrier to provide said plurality of contacts, prior to mounting said semiconductor die.
9. The process for fabricating the integrated circuit package according to claim 3 , first comprising selectively plating at least one layer of metal on said first surface of said metal carrier to provide said die attach pad and said plurality of contacts, prior to mounting said semiconductor die.
10. The process for fabricating the integrated circuit package according to claim 2 , wherein said placing said one of said metal carrier and said metal strip in said mold cavity comprises placing said metal strip in said mold cavity such that said metal strip rests on a lower die of said mold and said releasably clamping comprises releasably clamping said metal carrier to an upper die of said mold.
11. The process according to claim 9 , wherein said selectively plating comprises:
depositing a plating mask on said first surface of said metal carrier;
imaging and developing said plating mask to thereby expose portions of said metal carrier for plating said die attach pad and said contacts; and
plating at least one metal layer on portions of said first surface of said metal carrier exposed by said imaging and developing to provide said die attach pad and said contacts.
12. The process according to claim 9 , wherein selectively plating comprises selectively plating layers of gold, nickel and copper on said first surface of said metal carrier.
13. The process according to claim 1 , wherein said metal carrier has a coefficient of thermal expansion that is about equal to a coefficient of thermal expansion of the metal strip.
14. The process according to claim 1 , wherein the metal carrier is fabricated from a same metal as the metal strip.
15. A process for fabricating a plurality of integrated circuit packages, comprising:
mounting a plurality of semiconductor dice on a first surface of a metal carrier and forming electrical connections between said semiconductor dice and respective ones of a plurality of contacts on said metal carrier;
molding using a molding material in a mold to thereby mold the semiconductor dice and the contacts in the molding material, between said metal carrier and a metal strip;
etching away said metal carrier and said metal strip; and singulating said integrated circuit packages.
16. The process for fabricating the plurality of integrated circuit packages according to claim 15 , further comprising:
placing one of said metal carrier and said metal strip in a mold cavity in the mold; and
releasably clamping the other of said metal carrier and said metal strip to a die of said mold, prior to molding in said molding material.
17. The process for fabricating the plurality of integrated circuit packages according to claim 15 , wherein said semiconductor dice are mounted to respective die attach pads on said first surface of said metal carrier.
18. The process for fabricating the plurality of integrated circuit packages according to claim 17 , wherein said mounting said semiconductor die further comprises wire bonding said semiconductor dice to respective ones of the contacts.
19. The process for fabricating the plurality of integrated circuit packages according to claim 15 , wherein said semiconductor dice are directly mounted to said first surface of said metal carrier.
20. The process for fabricating the plurality of integrated circuit packages according to claim 19 , wherein said mounting said semiconductor dice further comprises wire bonding said semiconductor dice to respective ones of the contacts.
21. The process for fabricating the plurality of integrated circuit packages according to claim 15 , wherein mounting said semiconductor dice comprises flip-chip mounting said semiconductor dice to said respective ones of said plurality of contacts to thereby form said electrical connections.
22. The process for fabricating the plurality of integrated circuit packages according to claim 15 , first comprising selectively plating at least one layer of metal on said first surface of said metal carrier to provide said plurality of contacts, prior to mounting said semiconductor dice.
23. The process for fabricating the plurality of integrated circuit packages according to claim 17 , first comprising selectively plating at least one layer of metal on said first surface of said metal carrier to provide said die attach pads and said plurality of contacts, prior to mounting said semiconductor dice.
24. The process for fabricating the plurality of integrated circuit packages according to claim 16 , wherein said placing said one of said metal carrier and said metal strip in said mold cavity comprises placing said metal strip in said mold cavity such that said metal strip rests on a lower die of said mold and said releasably clamping comprises releasably clamping said metal carrier to an upper die of said mold.
25. The process according to claim 15 , wherein said metal carrier has a coefficient of thermal expansion that is about equal to a coefficient of thermal expansion of the metal strip.
26. The process according to claim 15 , wherein the metal carrier is fabricated from a same metal as the metal strip.