Offset-bonded, multi-chip semiconductor device
View Patent ↗The present invention is aimed at bonding a lower chip and an upper chip through bumps in a highly reliable manner, while ensuring a sufficient area for an external connection terminal region, by offsetting the upper chip to the lower chip. The substrate 2 has bumps 1 arranged on one surface thereof, and has a first chip 3 mounted on the other surface thereof. A second chip 4 is bonded to the first chip 3 through bumps 5, 6 while offsetting the second chip 4 to the first chip 3 in parallel. In the bonded state of the first chip 3 and the second chip 4, a part of the first chip 3 and a part of the second chip 4 are overlapped without aligning the centers of the both. The center of gravity of the second chip 4 falls inside a region surrounded by the outermost bumps between the first chip 3 and the second chip 4.
1. A semiconductor device comprising:
a first semiconductor element and a second semiconductor element stacked thereon without aligning a center of the first semiconductor element with a center of the second semiconductor element; and
electrodes formed on said first semiconductor element being connected through bumps to electrodes formed on said second semiconductor element in the overlapped region,
wherein a center of gravity of said second semiconductor element falls inside a first bump area surrounded by the outermost bumps out of said bumps bonding said first semiconductor element and said second semiconductor element.
2. The semiconductor device according to claim 1 , wherein the center of said first bump area and the center of gravity of said second semiconductor element coincide with each other.
3. The semiconductor device according to claim 1 , wherein said first bump area comprises three bump groups comprising those for input/output, those for power supply and those for grounding.
4. The semiconductor device according to claim 1 , wherein said second semiconductor element is a memory chip.
5. The semiconductor device according to claim 1 , wherein said first bump area comprises bump groups formed symmetrically at least about a single axis on the basis of the center line of said second semiconductor element.
6. The semiconductor device according to claim 1 , wherein said first semiconductor element has a plurality of external connection terminals arranged in a region thereof outside the overlapped region with said second semiconductor element, said plurality or external connection terminals being arranged in a staggered manner.
7. The semiconductor device according to claim 1 , wherein a third semiconductor element is stacked on said second semiconductor element, so that the center of gravity of said third semiconductor element coincides with the center of gravity of said second semiconductor element.
8. The semiconductor device according to claim 1 , wherein a plurality of semiconductor elements are stacked on said second semiconductor element, so that each of the centers of gravity of said plurality of semiconductor elements respectively coincides with the center of said second semiconductor element.
9. The semiconductor device according to claim 1 , wherein said first semiconductor element and said second semiconductor element are bonded such that one end face of said second semiconductor element overlaps at least one end face of said first semiconductor element.
10. A semiconductor device comprising:
a first semiconductor element and a second semiconductor element stacked thereon without aligning a center of the first semiconductor element with a center of the second a semiconductor element such that one end face of said second semiconductor element overlaps at least one end face of said first semiconductor element;
electrodes formed on said first semiconductor element being connected through bumps to electrodes formed on said second semiconductor element in the overlapped region; and
a dummy chip being arranged under the run-over region of said second semiconductor element, and said electrodes formed on said second semiconductor element being bonded through bumps to electrodes formed on said dummy chip,
wherein a center of gravity of said second semiconductor element falls inside a region including a maximized area which is determined by connecting the outermost bumps in a first bump area and the outermost bumps in a second bump area so as to include the entire portions of the individual bump areas, said first bump area being surrounded by the outermost bumps bonding said first semiconductor element and said second semiconductor element, and said second bump area being surrounded by the outermost bumps bonding said second semiconductor element and said dummy chip.
11. The semiconductor device according to claim 10 , wherein said first bump area comprises three bump groups comprising those for input/output, those for power supply and those for grounding.
12. The semiconductor device according to claim 10 , wherein said second semiconductor element is a memory chip.
13. The semiconductor device according to claim 10 , wherein said first bump area comprises bump groups formed symmetrically at least about a single axis on the basis of the center line of said second semiconductor element.
14. The semiconductor device according to claim 10 , wherein said first semiconductor element has a plurality of external connection terminals arranged in a region thereof outside the overlapped region with said second semiconductor element, said plurality or external connection terminals being arranged in a staggered manner.
15. The semiconductor device according to claim 10 , wherein a third semiconductor element is stacked on said second semiconductor element, so that the center of gravity of said third semiconductor element coincides with the center of gravity of said second semiconductor element.
16. The semiconductor device according to claim 10 , wherein a plurality of semiconductor elements are stacked on said second semiconductor element, so that each of the centers of gravity of said plurality of semiconductor elements respectively coincides with the center of said second semiconductor element.
17. The semiconductor device according to claim 10 , wherein said dummy chip is composed of a material having a thermal expansion coefficient close to that of the first semiconductor element.
18. The semiconductor device according to claim 17 , wherein said dummy chip is composed of Si.
19. The semiconductor device according to claim 10 , wherein thickness of said dummy chip falls between a maximum value and a minimum value, said maximum value being defined by a sum of thickness of said first semiconductor element and height-before-bonding of said bumps formed on said first semiconductor element, and said minimum value being defined by a balance obtained by subtracting the height-before-bonding of said bumps from distance-after-bonding between the back surface of said first semiconductor element and the top surface of said first semiconductor element.
20. The semiconductor device according to claim 10 , wherein said dummy chip has a metal film formed on the surface thereof.
21. The semiconductor device according to claim 20 , wherein said metal film comprises a Cr film and an Au film formed thereon.
22. The semiconductor device according to claim 10 , wherein the thickness of said dummy chip is equivalent to the thickness of said first semiconductor element.
23. The semiconductor device according to claim 8 , wherein a plurality of semiconductor elements are provided with through-holes through which the electrodes on a top surface and a back surface of the semiconductor elements are connected, and a plurality of the semiconductor elements are connected through the bumps.
24. The semiconductor device according to claim 16 , wherein a plurality of semiconductor elements are provided with through-holes through which the electrodes on a top surface and a back surface of the semiconductor elements are connected, and a plurality of the semiconductor elements are connected through the bumps.