Synchronization of multiple test instruments
View Patent ↗A test apparatus has multiple instruments that are synchronized with respect to one another so that a trigger signal may be generated in response to events occurring at different instruments. The events may correspond to events defined within a test program or events detected at a device under test. A partial trigger signal is generated by each of the different instruments, and the partial trigger signals are used in generating the trigger signal. Different offset delays are applied to the partial trigger signals so that the partial trigger signals generated by the different instruments are synchronized with respect to each other.
1. An apparatus having a plurality of test modules that operate to test an electronic device, comprising:
a first test module for generating test signals for the electronic device, the first test module having a device programmed to generate a first partial trigger signal and to delay the first partial trigger signal by a first delay amount; and
a second test module for generating test signals for the electronic device, the second test module having a device programmed to generate a second partial trigger signal and to delay the second partial trigger signal by a second delay amount,
wherein the first delay amount comprises a pipeline delay component and the second delay amount comprises a pipeline delay component, and wherein the pipeline delay component of the first delay amount differs from the pipeline delay component of the second delay amount by an amount that is equal to a difference in actual pipeline delays of the programmed devices of the first and second test modules, and
wherein a confirmed trigger signal is generated from at least the first and second partial trigger signals.
2. The apparatus according to claim 1 , wherein the first delay amount further comprises a hardware overhead component and the second delay amount further comprises a hardware overhead component, and wherein the hardware overhead component of the first delay amount differs from the hardware overhead component of the second delay amount by an amount that is equal to a difference in actual hardware overheads associated with partial trigger signal generation by the first and second test modules.
3. The apparatus according to claim 1 , further comprising:
a third test module for generating test signals for the electronic device, the third test module having a device programmed to execute a test sequence that includes a conditional part that is not executed until the confirmed trigger signal is received and to delay the execution of the conditional part after the confirmed trigger signal is received by a third delay amount; and
a fourth test module for generating test signals for the electronic device, the fourth test module having a device programmed to execute a test sequence that includes a conditional part that is not executed until the confirmed trigger signal is received and to delay the execution of the conditional part after the confirmed trigger signal is received by a fourth delay amount.
4. The apparatus according to claim 3 , wherein test signals generated by the third test module upon execution of the conditional part and test signals generated by the fourth test module upon execution of the conditional part arrive at the electronic device simultaneously.
5. The apparatus according to claim 4 , wherein each of the programmed devices of the third and fourth test modules includes a counter based on which the third delay amount and the fourth delay amount are adjusted.
6. An apparatus having a plurality of test modules that operate to test an electronic device, comprising:
a first test module for generating test signals for the electronic device, the first test module having a device programmed to generate a first partial trigger signal in response to a detection signal that is generated based on a first event detected at the electronic device and delayed by a first delay amount; and
a second test module for generating test signals for the electronic device, the second test module having a device programmed to generate a second partial trigger signal in response to a detection signal that is generated based on a second event detected at the electronic device and delayed by a second delay amounts,
wherein the first delay amount comprises a pipeline delay component and the second delay amount comprises a pipeline delay component, and wherein the pipeline delay component of the first delay amount differs from the pipeline delay component of the second delay amount by an amount that is equal to a difference in actual pipeline delays of the programmed devices of the first and second test modules, and
wherein a confirmed trigger signal is generated from at least the first and second partial trigger signals.
7. The apparatus according to claim 6 , wherein the first delay amount further comprises a device response delay component and the second delay amount further comprises a device response delay component, wherein the device response delay component of the first delay amount differs from the device response delay component of the second delay amount by an amount that is equal to a difference in actual device response delays associated with the first and second test modules.
8. The apparatus according to claim 6 , further comprising:
a third test module for generating test signals for the electronic device, the third test module having a device programmed to execute a test sequence that includes a conditional part that is not executed until the confirmed trigger signal is received and to delay the execution of the conditional part after the confirmed trigger signal is received by a third delay amount; and
a fourth test module for generating test signals for the electronic device, the fourth test module having a device programmed to execute a test sequence that includes a conditional part that is not executed until the confirmed trigger signal is received and to delay the execution of the conditional part after the confirmed trigger signal is received by a fourth delay amount.
9. The apparatus according to claim 8 , wherein test signals generated by the third test module upon execution of the conditional part and test signals generated by the fourth test module upon execution of the conditional part arrive at the electronic device at the same time.
10. The apparatus according to claim 9 , wherein each of the programmed devices of the third and fourth test modules includes a counter based on which the third delay amount and the fourth delay amount are adjusted.
11. A method of issuing a trigger signal based on a first partial trigger signal generated at a first test instrument and a second partial trigger signal generated at a second test instrument during test of an electronic device, comprising the steps of:
delaying generation of the first partial trigger signal by a first delay amount;
delaying generation of the second partial trigger signal by a second delay amount; and
generating the trigger signal based on the first and second partial trigger signals,
wherein the first delay amount comprises a pipeline delay component and the second delay amount comprises a pipeline delay component, and wherein the pipeline delay component of the first delay amount differs from the pipeline delay component of the second delay amount by an amount that is equal to a difference in actual pipeline delays of the first and second test instruments.
12. The method according to claim 11 , wherein the first delay amount further comprises a hardware overhead component and the second delay amount further comprises a hardware overhead component, wherein the hardware overhead component of the first delay amount differs from the hardware overhead component of the second delay amount by an amount that is equal to a difference in actual hardware overheads associated with partial trigger signal generation by the first and second test instruments.
13. The method according to claim 11 , wherein the first delay amount further comprises a device response delay component and the second delay amount further comprises a device response delay component, wherein the device response delay component of the first delay amount differs from the device response delay component of the second delay amount by an amount that is equal to a difference in actual device response delays associated with the first and second test instruments.
14. The method according to claim 11 , further comprising the steps of:
when the trigger signal is received at a third test instrument, delaying execution of test instructions by a third delay amount; and
when the trigger signal is received at a fourth test instrument, delaying execution of test instructions by a fourth delay amount.
15. The method according to claim 14 , wherein test signals generated by the third test instrument upon execution of the test instructions and test signals generated by the fourth test instrument upon execution of the test instructions arrive at the electronic device at the same time.
16. The method according to claim 15 , further comprising the step of counting clock cycles at the third and fourth test instruments, and adjusting the third and fourth delay amounts based on the counted clock cycles.
17. The method according to claim 11 , further comprising the steps of performing an arithmetic AND operation on the first and second partial trigger signals and generating the trigger signal based on the result of the arithmetic AND operation.