IP Library Granted Patent US 7,095,107
Granted Patent B2
US 7,095,107 · App. 11/005,732 · Granted Aug 22, 2006

Ball assignment schemes for integrated circuit packages

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Quick Facts
Patent No.
US 7,095,107
App. No.
11/005,732
Granted
Aug 22, 2006
Kind
B2
Abstract

The present disclosure is directed to ball assignment schemes for ball grid array packages in integrated circuits with increased signal count. The ball assignment scheme includes an array of electrical contacts. The array has a first diagonal including a pair of signal contacts adjacent to a pair of first-type voltage supply contacts. The array further includes a crossing diagonal having a pair of adjacent second-type voltage supply contacts, which crosses the first diagonal between the pair of signal contacts such that the pair of second-type voltage supply contacts oppose one another relative to the first diagonal.

Claims (31)

1. A grid array of electrical contacts in an integrated circuit package, the grid array comprising:

a first diagonal including a pair of adjacent signal contacts and an adjacent a pair of adjacent first-type voltage supply contacts; and

a crossing diagonal including a pair of adjacent second-type voltage supply contacts, which crosses the first diagonal between the pair of signal contacts such that the pair of second-type voltage supply contacts oppose one another relative to the first diagonal.

2. The grid array of claim 1 wherein the first-type voltage supply contacts are ground contacts and the second-type voltage supply contacts are power contacts.

3. The grid array of claim 1 wherein the first diagonal is orthogonal to the crossing diagonal.

4. The grid array of claim 1 wherein the first diagonal comprises a repeating pattern of pairs of adjacent signal contacts interleaved with pairs of adjacent first-type voltage supply contacts along the first diagonal.

5. The array of claim 4 wherein array further comprises:

a plurality of crossing diagonals, including the first-mentioned crossing diagonal, each crossing diagonal including a pair of adjacent second-type voltage supply contacts, which crosses the first diagonal between a corresponding pair of signal contacts.

6. The grid array of claim 1 wherein the grid array includes a plurality of spaced-apart and parallel first diagonals.

7. The grid array of claim 6 and further comprising:

a plurality of second diagonals located between and parallel to the first diagonals, each second diagonal including a plurality of signal contacts distributed along the second diagonal.

8. The grid array of claim 7 and further comprising:

the second diagonals that are immediately adjacent the first diagonals further include the second-type voltage supply contacts, which are distributed along the second diagonal such that pairs of the second-type voltage supply contacts oppose one another relative to the corresponding first diagonal and form the crossing diagonals.

9. The grid array of claim 7 wherein there are three second diagonals between each corresponding pair of the first diagonals.

10. The grid array of claim 7 wherein there are four second diagonals between each corresponding pair of the first diagonals.

11. The grid array of claim 1 wherein the integrated circuit package includes a flip chip.

12. An array of electrical contacts on a substrate, the array comprising:

a plurality of parallel and spaced-apart first diagonals, each first diagonal including signal contacts and first-type voltage supply contacts distributed along the first diagonal; and

a plurality of second diagonals located between and parallel to the first diagonals, each second diagonal including a plurality of signal contacts, wherein the second diagonals that are adjacent the first diagonals further include second-type voltage supply contacts distributed along the second diagonal such that pairs of the second-type voltage supply contacts oppose one another relative to the corresponding first diagonal.

13. The array of claim 12 wherein each of the signal contacts in the array is located within one contact position from a nearest first-type voltage supply contact and a nearest second-type voltage supply contact.

14. The array of claim 12 wherein each of the first diagonals comprises a repeating pattern of pairs of adjacent signal contacts interleaved with pairs of adjacent first-type voltage supply contacts along the first diagonal.

15. The array of claim 14 wherein the pairs of the second-type voltage supply contacts that oppose one another relative to the corresponding first diagonal form a crossing diagonal, which crosses the first diagonal between a corresponding pair of the signal contacts in the first diagonal.

16. The array of claim 12 wherein there are three second diagonals between each corresponding pair of the first diagonals.

17. The array of claim 12 wherein there are four second diagonals between each corresponding pair of the first diagonals.

18. The array of claim 12 wherein the first-type of voltage supply contacts are ground contacts and the second-type of voltage supply contacts are power contacts.

19. A grid array of electrical contacts in an integrated circuit package, the grid array comprising:

a plurality of adjacent grid boxes;

wherein each grid box including sixteen electrical contacts arranged in a four rows of four contacts;

wherein the sixteen electrical contacts in each grid box include twelve signal contacts, two ground contacts along a first diagonal, and two power contacts along a second diagonal; and

wherein the first diagonal crosses the second diagonal in the grid box.

20. The grid array of claim 19 wherein the two ground contacts in each grid box are spaced-apart from each other by two adjacent signal contacts on the first diagonal; and wherein the two power contacts are adjacent to each other and spaced-apart by two signal contacts along the second diagonal in each grid box.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jun 11, 2020
From: ROYAL BANK OF CANADA
To: TESSERA, INC.; INVENSAS BONDING TECHNOLOGIES, INC. (F/K/A ZIPTRONIX, INC.); FOTONATION CORPORATION (F/K/A DIGITALOPTICS CORPORATION AND F/K/A DIGITALOPTICS CORPORATION MEMS); INVENSAS CORPORATION; TESSERA ADVANCED TECHNOLOGIES, INC; DTS, INC.; DTS LLC; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
Reel/Frame 052920/0001 →
SECURITY INTEREST Recorded Dec 2, 2016
From: INVENSAS CORPORATION; TESSERA, INC.; TESSERA ADVANCED TECHNOLOGIES, INC.; ZIPTRONIX, INC.; DIGITALOPTICS CORPORATION; DIGITALOPTICS CORPORATION MEMS; DTS, LLC; DTS, INC.; PHORUS, INC.; IBIQUITY DIGITAL CORPORATION
To: ROYAL BANK OF CANADA, AS COLLATERAL AGENT
Reel/Frame 040797/0001 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME, PREVIOUSLY RECORDED ON REEL 023778 FRAME 0177. Recorded Feb 24, 2010
From: LSI CORPORATION
To: TESSERA, INC.
Reel/Frame 023985/0861 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 13, 2010
From: LSI LOGIC CORPORATION
To: TESSERA, INC.
Reel/Frame 023778/0177 →
CHANGE OF NAME Recorded Nov 19, 2009
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 023546/0137 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2004
From: RAMAKRISHNAN, ARUN; GOVIND, ANAND
To: LSI LOGIC CORPORATION
Reel/Frame 016073/0458 →