Oscillator circuit operating with a variable driving voltage

1. An oscillator operating with a variable driving voltage to produce an oscillation signal of a predetermined period, the oscillator having a plurality of logic devices connected to each other in a form of a ring, the oscillator comprising:

a voltage generating circuit, that generates first and second driving voltages which are selectively applied to the logic devices, said second driving voltages being higher than the first driving voltages when the oscillation signal period is shorter than the predetermined period;

wherein the selective application of the first or second driving voltage to the logic devices affects the period of the oscillation signal produced; and

further wherein the first driving voltage is applied to the logic devices for normal operations when the oscillation signal period is substantially equal the predetermined period or the second driving voltage is applied to the logic devices for normal operations when the oscillation signal period is different from the predetermined period.

2. The oscillator of claim 1 further comprising: means for adjusting the second driving voltage having at least two resistors.

3. The oscillator of claim 1 , wherein the second driving voltage is lower than the first driving voltage when the oscillation signal period is longer than the predetermined period.

4. The oscillator of claim 1 , wherein the logic devices connected to each other in the form of a ring include inverters.

5. The oscillator of claim 1 , wherein the voltage generating circuit comprises one or more of driving voltage generating units, wherein each driving voltage generating unit comprises: a reference voltage generator for generating a first reference voltage; a level shifter circuit for receiving the first reference voltage and outputting a second reference voltage; and a driving unit for receiving the second reference voltage and outputting a first driving signal having an electric potential level substantially identical to that of the second reference voltage, wherein the first driving signal is available for use as the first or second driving voltage to the logic devices.

6. The oscillator as claimed in claim 4 , wherein the level shifter circuit comprises:

a first NMOS transistor receiving the first reference voltage through a first NMOS gate terminal;

first, second, and third PMOS transistors receiving a supply voltage through the source terminal of each of the first, second, and third PMOS transistors,

wherein the gate terminal of the first PMOS transistor is connected to the gate terminal of the second PMOS transistor, the gate and source terminals of the second PMOS transistor are connected, the drain terminal of the first PMOS transistor is connected to the drain terminal of the first NMOS transistor, the drain terminal of the first NMOS transistor is connected to the gate terminal of the third PMOS transistor;

a second NMOS transistor connected between a drain terminal of the second PMOS transistor and a source terminal of the first NMOS transistor,

wherein the drain terminal of the second PMOS transistor is connected to the drain terminal of the second NMOS transistor, the source terminal of the first NMOS transistor is connected to the source terminal of the second NMOS transistor,

a third NMOS transistor receiving a bias voltage through a third NMOS transistor gate terminal, wherein the third NMOS transistor is connected between the source terminal of the first NMOS transistors and the ground;

a first resistance element connected between a drain terminal of the third PMOS transistor and the second NMOS transistor gate terminal; and

a second resistance element connected between the second NMOS transistor gate terminal and the ground,

wherein the drain terminal of the third PMOS transistor outputs the driving voltage of the driving voltage generating unit.

7. The oscillator as claimed in claim 6 , wherein the driving voltage of the driving voltage generating unit is regulated by changing the resistance ratio of the first and second resistance elements.

8. An oscillator operating with a variable driving voltage to produce an oscillation signal of a predetermined period, the oscillator having a plurality of logic devices connected to each other in a form of a ring, the oscillator comprising:

a voltage generating means for generating first and second driving voltages which are selectively applied to the logic devices,

wherein the selective application of the first or second driving voltage to the logic devices affects the period of the oscillation signal produced, the voltage generating means further comprising:

a first driving voltage generating unit generating the first driving voltage; and

a second driving voltage generating unit generating the second driving voltage, the second driving voltage generating unit including the voltage regulating means for regulating the level of the second driving voltage,

wherein either the first driving voltage is applied to the logic devices for normal operations when the oscillation signal period is substantially equal the predetermined period or the second driving voltage is applied to the logic devices for normal operations when the oscillation signal is different from the predetermined period.

9. The oscillator of claim 8 , wherein the voltage regulating means includes at least first and second resistance elements and wherein the electric potential level of the second driving voltage is regulated by varying the resistance ratio between at least first and second resistance elements in the voltage regulating means.

10. The oscillator of claim 9 , wherein the second driving voltage is regulated to be higher than the first driving voltage by adjusting the resistance ratio when the oscillation signal period is shorter than the predetermined period.

11. The oscillator of claim 9 , wherein the second driving voltage is regulated to be lower than the first driving voltage by adjusting the resistance ratio when the oscillation signal period is longer than the predetermined period.

12. The oscillator of claim 9 , wherein the first driving voltage generating unit comprises:

a first level shifter circuit for receiving a first reference voltage and generating a second reference voltage; and

a first driving unit for receiving the second reference voltage and generating the first driving voltage,

wherein the first driving unit regulates the first driving voltage to substantially equal the second reference voltage.

13. The oscillator of claim 12 , wherein the first level shifter circuit comprises:

a first NMOS transistor receiving the first reference voltage through a first NMOS gate terminal:

first, second, and third PMOS transistors receiving a supply voltage through the source terminal of each of the first, second, and third PMOS transistors,

wherein the gate terminal of the first PMOS transistor is connected to the gate terminal of the second PMOS transistor, the gate and source terminals of the second PMOS transistor are connected, the drain terminal of the first PMOS transistor is connected to the drain terminal of the first NMOS transistor, the drain terminal of the first NMOS transistor is connected to the gate terminal of the third PMOS transistor; a second NMOS transistor connected between a drain terminal of the second PMOS transistor and a source terminal of the first NMOS transistor,

wherein the drain terminal of the second PMOS transistor is connected to the drain terminal of the second NMOS transistor, the source terminal of the first NMOS transistor is connected to the source terminal of the second NMOS transistor;

a third NMOS transistor receiving a bias voltage through a third NMOS transistor gate terminal, wherein the third NMOS transistor is connected between the source terminal of the first NMOS transistors and the ground;

a third resistance element connected between a drain terminal of the third PMOS transistor and the second NMOS transistor gate terminal; and

a fourth resistance element connected between the second NMOS transistor gate terminal and the ground, wherein the drain terminal of the third PMOS transistor outputs the second reference voltage.

14. The oscillator of claim 9 , wherein the second driving voltage generating unit comprises:

a second level shifter circuit for receiving a first reference voltage and generating a third reference voltage; and

a second driving unit for receiving the third reference voltage and generating the second driving voltage,

wherein the second driving unit regulates the second driving voltage to substantially equal the third reference voltage.

15. The oscillator of claim 12 , wherein the second level shifter circuit comprises:

a fourth NMOS transistor receiving the first reference voltage through a fourth NMOS gate terminal;

fourth, fifth, and sixth PMOS transistors receiving a supply voltage through the source terminal of each of the fourth, fifth, and sixth PMOS transistors,

wherein the gate terminal of the fourth PMOS transistor is connected to the gate terminal of the fifth PMOS transistor, the gate and source terminals of the fifth PMOS transistor are connected, the drain terminal of the fourth PMOS transistor is connected to the drain terminal of the fourth NMOS transistor, the drain terminal of the fourth NMOS transistor is connected to the gate terminal of the sixth PMOS transistor; a fifth NMOS transistor connected between a drain terminal of the fifth PMOS transistor and a source terminal of the fourth NMOS transistor,

wherein the drain terminal of the fifth PMOS transistor is connected to the drain terminal of the fifth NMOS transistor, the source terminal of the fourth NMOS transistor is connected to the source terminal of the fifth NMOS transistor;

a sixth NMOS transistor receiving a bias voltage through a sixth NMOS transistor gate terminal, wherein the sixth NMOS transistor is connected between the source terminal of the fourth NMOS transistors and the ground;

the first resistance element connected between a drain terminal of the sixth PMOS transistor and the fifth NMOS transistor gate terminal; and

the third resistance element connected between the fifth NMOS transistor gate terminal and the ground, wherein the drain terminal of the sixth PMOS transistor outputs the third reference voltage.