Method of reading multi-level NAND flash memory cell and circuit for the same
View Patent ↗The disclosed is a method of reading a multi-level NAND flash memory cell and a circuit for the same. The read circuit for the NAND flash memory device includes a NAND flash memory cell having multi-level information, a first page buffer for storing an upper-bit, a second page buffer for storing a lower bit, and pass transistor for changing information of the second page buffer according to a variation of the first page buffer. In accordance with the present invention, “00” or “01” information is read out by applying a first voltage to a word line of the cell. “00”, “01”, or “11” information is read out by applying a second voltage to the word line. A latch pass control signal is applied to a pass transistor. Thus, it is possible to read out “00”, “01”, “11”, or “10” information.
1. A read circuit for a multi-level NAND flash memory comprising:
a cell string where plural cells for storing multi-level information are connected serially;
plural word lines connected to a gate terminal of each cell string;
a bit line connected to a drain terminal of the cell string;
a first page buffer having a first latch for storing upper-bit information among information of a cell selected by the word line and the bit line, and a second page buffer having a second latch for storing lower bit information of the selected cell; and
a pass unit connected between the first latch and the second latch and driven according to a latch pass control signal so that information of the second latch is changed by information of the first latch.
2. The read circuit for a multi-level NAND flash memory as set forth in claim 1 , further comprising:
a drain selection transistor connected between the drain terminal of the cell string and the bit line to be driven according to a drain selection signal;
a source selection transistor connected between the source terminal of the cell string and a common ground line to be driven according to a source selection signal; and
a discharge transistor for discharging the bit line according to a predetermined discharge signal.
3. The read circuit for a multi-level NAND flash memory as set forth in claim 1 , further comprising:
first and second drain selection transistors connected between the drain terminal of the first cell string and an even bit line, and between the drain terminal of the second cell string and an odd bit line to be driven according to a drain selection signal;
first and second source selection transistors respectively connected between the source terminal of the first and second cell strings and a common ground line to be driven according to a source selection signal; and
first and second discharge transistors discharging the even or odd bit line according to an even or odd discharge signal.
4. The read circuit for a multi-level NAND flash memory as set forth in claim 1 , wherein the first page buffer comprises:
a bit decision node receiving a predetermined signal from the bit line or transferring the predetermined signal to the bit line;
the first latch storing predetermined data;
a PMOS transistor transferring a predetermined precharge voltage to the bit decision node according to a precharge signal;
a first transistor transfening data stored in the first latch according to a program signal to the bit decision node; and
second and third transistors connected between the first latch and a ground power to respectively change the data of the first latch according to the bit decision node signal and an upper-bit latch signal.
5. The read circuit for a multi-level NAND flash memory as set forth in claim 1 , wherein the second page buffer comprises:
a bit decision node receiving a predetermined signal from the bit line or transferring the predetermined signal to the bit line;
the second latch storing predetermined data;
a PMOS transistor transferring a predetermined precharge voltage to the bit decision node according to a precharge signal;
a first transistor transferring data stored in the second latch according to a program signal to the bit decision node; and
second and third transistors connected between the second latch and a ground power to respectively change the data of the latch according to the bit decision node signal and a lower bit latch signal.
6. The read circuit for a multi-level NAND flash memory as set forth in claim 1 , wherein the pass unit includes:
a pass transistor connected between the first latch and the second latch to be driven according to the latch pass control signal; and
a pass inverter connected between the pass transistor and the second latch.
7. A read circuit for a multi-level NAND flash memory comprising:
first and second cell strings where plural cells for storing multi-level information are connected serially;
plural word lines connected to a gate terminal of each of the first and second cell strings;
even and odd bit lines connected to a drain terminal of the first and second cell strings;
first and second bit line selection transistors selecting one of bit line among the even or odd bit line according to a bit line selection signal;
a first page buffer having a first latch and connected to the first and second bit line selection transistors to store upper-bit information among information of a selected cell;
a second page buffer having a second latch and connected to the first and second bit line selection transistors to store lower bit information among information of a selected cell; and
a pass unit connected between the first latch and the second latch and driven according to a latch pass control signal so that information of the second latch is changed by information of the first latch.
8. The read circuit for a multi-level NAND flash memory as set forth in claim 7 , wherein the first page buffer comprises:
a bit decision node receiving a predetermined signal from the bit line or transferring the predetermined signal to the bit line;
the first latch storing predetermined data;
a PMOS transistor transferring a predetermined precharge voltage to the bit decision node according to a precharge signal;
a first transistor transferring data stored in the first latch according to a program signal to the bit decision node; and
second and third transistors connected between the first latch and a ground power to respectively change the data of the first latch according to the bit decision node signal and an upper-bit latch signal.
9. The read circuit for a multi-level NAND flash memory as set forth in claim 7 , wherein the second page buffer comprises:
a bit decision node receiving a predetermined signal from the bit line or transferring the predetermined signal to the bit line;
the second latch storing predetermined data;
a PMOS transistor transferring a predetermined precharge voltage to the bit decision node according to a precharge signal;
a first transistor transferring data stored in the second latch according to a program signal to the bit decision node; and
second and third transistors connected between the second latch and a ground power to respectively change the data of the latch according to the bit decision node signal and a lower bit latch signal.
10. The read circuit for a multi-level NAND flash memory as set forth in claim 7 , wherein the pass unit includes:
a pass transistor connected between the first latch and the second latch to be driven according to the latch pass control signal; and
a pass inverter connected between the pass transistor and the second latch.
11. A read circuit for a multi-level NAND flash memory including a cell string where plural cells for storing multi-level information are connected serially; a bit line connected to a drain terminal of the cell string; a first page buffer for storing upper-bit information among information of a cell selected by the word line and the bit line, and a second page buffer for storing lower bit information of the selected cell; and a pass unit driving the second page buffer to change information of the second page buffer, the read circuit comprises the steps of:
resetting the first and second page buffers;
applying a first voltage to the selected word line, reading data stored in the cell by a reading operation, and then storing the second page buffer according to the lower bit latch signal;
applying a second voltage to the selected word line, reading data stored in the cell by the reading operation, and then storing the first page buffer according to the upper-bit latch signal; and
storing logic low data to the second page buffer by driving the second page buffer through the pass unit if logic high data is stored in the first page buffer according to the upper-bit latch signal and the latch pass control signal by reading data stored in the cell through the reading operation after applying a third voltage to the selected word line.
12. The read circuit for a multi-level NAND flash memory as set forth in claim 11 , wherein the reading operation comprises the steps of:
applying a logic high precharge voltage to the bit line through the first or second page buffer;
waiting that a charge of the precharge voltage applied to the bit line discharges or is holding after cutting off a current flow between the first or second page buffer and the bit line;
transferring a voltage state of the bit line to the first and second page buffers.
13. The read circuit for a multi-level NAND flash memory as set forth in claim 11 , wherein data stored in the selected cell is read by applying the first voltage to the word line and applying the lower bit latch signal, and
wherein storage data of the first page buffer is maintained logic “0” being a reset state, and
wherein storage data of the second page buffer is maintained logic “0” or is changed to logic “1”.
14. The read circuit for a multi-level NAND flash memory as set forth in claim 11 , wherein data stored in the selected cell is read by applying the second voltage to the word line and the upper-bit latch signal, and
wherein the storage data of the first page buffer is maintained in a previous logic state or is changed to logic “1”, and
wherein storage data of the second page buffer is maintained in a previous logic state.
15. The read circuit for a multi-level NAND flash memory as set forth in claim 11 , wherein data stored in the selected cell is read by applying the third voltage to the word line, the upper-bit latch signal, and the latch pass control signal, and
wherein the storage data of the first page buffer is maintained in a previous logic state or is changed to logic “1”, and
wherein the second page buffer is changed to logic “0” by the pass unit when data of the first page buffer is changed to logic “1”, and
wherein the second page buffer is maintained in a previous logic state in other cases.
16. The read circuit for a multi-level NAND flash memory as set forth in claim 11 , wherein a voltage interval of the first to third voltage is the same as an interval of a cell threshold voltage.
17. The read circuit for a multi-level NAND flash memory as set forth in claim 7 , further comprising:
first and second drain selection transistors connected between the drain terminal of the first cell string and the even bit line, and between the drain terminal of the second cell string and the odd bit line to be driven according to a drain selection signal;
first and second source selection transistors respectively connected between the source terminal of the first and second cell strings and a common ground line to be driven according to a source selection signal; and
first and second discharge transistors discharging the even or odd bit line according to an even or odd discharge signal.