Silicon-on-insulator channel architecture for automatic test equipment
View Patent ↗A channel architecture for use in automatic test equipment is disclosed. The channel architecture comprises pattern generation circuitry and timing circuitry responsive to the pattern generation circuitry to generate timing signals. Formatting circuitry coupled to the output of the timing circuitry generates pulse waveforms for application to pin electronics circuitry. The pin electronics circuitry is responsive to the formatting circuitry for interfacing the automatic test equipment to a device-under-test. The pattern generation circuitry, the timing circuitry, the formatting circuitry and the pin electronics circuitry are formed on the same integrated circuit.
1. A method of testing involving a semiconductor device, the method comprising the steps:
selecting automatic test equipment comprising a controller and a testhead, the testhead adapted for housing a plurality of channel cards, each channel card comprising a plurality of integrated circuit chips, each chip comprising
pattern generation circuitry,
timing circuitry responsive to the pattern generation circuitry to generate timing signals;
formatting circuitry coupled to the output of the timing circuitry to generate pulse waveforms, and
pin electronics circuitry responsive to the formatting circuitry for interfacing the automatic test equipment to a device-under-test; and
testing the semiconductor device with the selected automatic test equipment.
2. The method of testing involving a semiconductor device according to claim 1 wherein each chip is formed by a silicon-on-insulator process.
3. The method of testing involving a semiconductor device according to claim 1 , further comprising forming the pattern generation circuitry, the timing circuitry and the formatting circuitry to comprise low voltage digital circuits capable of operating at voltage levels no greater than one volt.
4. The method of testing involving a semiconductor device according to claim 1 , further comprising forming the pin electronics circuitry to comprise high-voltage analog circuits capable of operating at voltages higher than one volt.
5. The method of testing involving a semiconductor device according to claim 1 , further comprising forming each chip to include transistors without common bulk connections.
6. The method of testing involving a semiconductor device according to claim 1 , further comprising forming each chip to include transistors having voltage between a source voltage and ground divided equally between stacked transistors.
7. The method of testing involving a semiconductor device according to claim 1 , further comprising forming each chip to include transistors having a semiconductor layer including source, gate and drain terminals formed on top of a thin layer of silicon.
8. The method of testing involving a semiconductor device according to claim 1 , further comprising forming each chip using stacked transistors with low breakdown voltages.