IP Library Granted Patent US 7,135,881
Granted Patent B2
US 7,135,881 · App. 11/018,626 · Granted Nov 14, 2006

Method and system for producing signals to test semiconductor devices

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Quick Facts
Patent No.
US 7,135,881
App. No.
11/018,626
Granted
Nov 14, 2006
Kind
B2
Abstract

A method of and system for producing signals to test semiconductor devices includes a pin electronic (PE) stage for providing a parametric measurement unit (PMU) current test signal to a semiconductor device under test. The PE stage also senses a response from the semiconductor device under test.

Claims (33)

1. A semiconductor device tester comprising:

a pin electronics (PE) stage configured to provide alternating current (AC) and direct current (DC) test signals to a semiconductor device under test, the DC test signals including a first current signal, wherein the PE stage is also configured to sense a response from the semiconductor device under test; and

a parametric measurement unit (PMU) stage configured to provide DC test signals to the semiconductor device under test, the DC test signals including a second current signal, the first current signal containing a higher current level than the second current signal;

wherein the PMU stage comprises a selector configured to provide test current from the PMU stage to the PE stage where the test current is used to generate the second current signal.

2. The semiconductor device tester of claim 1 , wherein the sensed response includes a voltage that is present at the semiconductor device under test.

3. The semiconductor device tester of claim 1 , wherein the PE stage includes at least one current source.

4. The semiconductor device tester of claim 1 , wherein the PE stage is configured to produce a signal to represent the sensed response of the semiconductor device under test.

5. The semiconductor tester of claim 1 , wherein the PE stage operates at a higher speed than the PMU stage.

6. A semiconductor tester comprising:

a pin electronics (PE) stage configured to provide PE test signals to a semiconductor device under test, the PE test signals comprising alternating current (AC) and direct current (DC) test signals; and

a parametric measurement unit (PMU) stage configured to provide PMU test signals to the semiconductor device under test, the PMU test signals comprising only DC test signals;

wherein the PE stage operates at a higher speed than the PMU stage.

7. The semiconductor tester of claim 6 , wherein the PE stage includes a diode for producing the DC test signals.

8. The semiconductor tester of claim 6 , wherein the PE stage includes at least one current source for producing PE test signals that provide current.

9. The semiconductor tester of claim 6 , wherein the PE stage further comprises:

a comparator stage configured to receive a signal from the semiconductor device under test in response to a DC test signal output by the PE stage.

10. The semiconductor tester of claim 9 , wherein the received signal is a voltage signal.

11. The semiconductor tester of claim 9 , wherein the comparator stage includes an operational amplifier configured to compare the voltage signal to a first voltage.

12. The semiconductor tester of claim 9 , wherein the comparator stage is configured to provide a signal that represents a comparison of the received signal and a first voltage.

13. A semiconductor tester comprising:

a pin electronics (PE) current source configured to provide a first direct current (DC) current test signal to a semiconductor device under test;

a PE comparator stage configured to receive a response voltage from the semiconductor device under test in response to the first DC current test signal, and to compare the response voltage to a first voltage and a second voltage for identifying the response voltage;

a parametric measurement unit (PMU) driver circuit configured to provide a second DC test signal for testing the semiconductor device; and

a feedback circuit comprising (i) a first sense line to sense a DC test signal at an output of the PMU driver circuit and to provide a resulting sensed DC test signal to an input of the PMU driver circuit to allow for the compensation of the second DC test signal, and (ii) second sense lines to sense for monitoring current across a resistor at an output of the PMU driver circuit.

14. The semiconductor tester of claim 13 , wherein the first voltage is larger than the second voltage.

15. The semiconductor tester of claim 13 , wherein the PE current source includes a high-impedance output.

16. The semiconductor tester of claim 13 , wherein the PE comparator stage includes an amplifier for comparing the response voltage to the first voltage.

17. The semiconductor tester of claim 13 , further comprising:

a PE driver stage configured to provide a PE voltage test signal to the semiconductor device under test.

18. The semiconductor tester of claim 13 , further comprising:

PE circuitry configured to produce an alternating current (AC) test signal for testing the semiconductor device; and

a driver circuit configured to provide, in a first mode, a version of the second DC test signal to the semiconductor device and, in a second mode, configured to provide a version of the AC test signal to the semiconductor device.

19. The semiconductor tester of claim 13 , wherein PE circuitry operates at a higher speed than PMU circuitry.

Assignments (7)
SECURITY INTEREST Recorded May 7, 2020
From: TERADYNE, INC.
To: TRUIST BANK
Reel/Frame 052595/0632 →
RELEASE OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Jun 28, 2019
From: BARCLAYS BANK PLC, AS COLLATERAL AGENT
To: TERADYNE, INC.; EAGLE TEST SYSTEMS, INC.; LITEPOINT CORPORATION; NEXTEST SYSTEMS CORPORATION; GENRAD, LLC; ENERGID TECHNOLOGIES CORPORATION
Reel/Frame 049632/0940 →
PATENT SECURITY AGREEMENT Recorded Apr 27, 2015
From: TERADYNE, INC.; LITEPOINT CORPORATION
To: BARCLAYS BANK PLC
Reel/Frame 035507/0116 →
RELEASE OF SECURITY INTEREST Recorded May 13, 2009
From: BANK OF AMERICA, N.A.
To: TERADYNE, INC
Reel/Frame 022668/0750 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Dec 3, 2008
From: TERADYNE, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 021912/0762 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 12, 2005
From: WALKER, ERNEST; SARTSCHEV, RONALD A.
To: TERADYNE, INC.
Reel/Frame 016215/0538 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2005
From: WALKER, ERNEST; SARTSCHEV, RONALD A.
To: TERADYNE, INC.
Reel/Frame 016322/0368 →