Semiconductor device having layered chips
View Patent ↗A semiconductor device includes an interface chip and a plurality of DRAM chips consecutively layered on the interface chip. A plurality of source electrodes, a plurality of ground electrodes, and a plurality of signal electrodes penetrate DRAM chips and interconnect the DRAM chips to the interface chip, which is connected to an external circuit. Each source electrode, a corresponding signal electrode and a corresponding ground electrode are arranged adjacent to one another in this order to reduce electromagnetic noise during operation of the DRAM chip.
1. A semiconductor device comprising:
plural semiconductor chips layered one on another; and
plural inter-chip electrodes each penetrating at least one of said plural semiconductor chips and interconnecting at least two of said plural semiconductor chips,
said plural inter-chip electrodes including plural inter-chip power source electrodes, plural inter-chip ground electrodes and plural inter-chip signal electrodes,
wherein an electrode pair including one of said inter-chip power source electrodes and one of said inter-chip ground electrodes, which are immediately adjacent each other, is sandwiched between two of said inter-chip signal electrodes that are immediately adjacent said electrode pair,
wherein current flowing through said inter-chip power source electrode is opposite in direction to current flowing through said inter-chip ground electrode.
2. A semiconductor device comprising:
plural semiconductor chips layered one on another; and
plural inter-chip electrodes each penetrating at least one of said plural semiconductor chips and interconnecting at least two of said plural semiconductor chips,
said inter-chip electrodes including plural inter-chip power source electrodes, plural inter-chip ground electrodes and plural inter-chip signal electrodes,
wherein one of said inter-chip signal electrodes is sandwiched between two immediately adjacent electrode pairs each including one of said inter-chip power source electrodes and one of said inter-chip ground electrodes,
wherein current flowing through said inter-chip power source electrode is opposite in direction to current flowing through said inter-chip ground electrode.
3. A semiconductor device comprising:
plural semiconductor chips layered one on another; and
plural inter-chip electrodes each penetrating at least one of said plural semiconductor chips and interconnecting at least two of said plural semiconductor chips,
said inter-chip electrodes including plural inter-chip power source electrodes, plural inter-chip ground electrodes and plural inter-chip signal electrodes,
wherein an electrode pair including one of said inter-chip power source electrodes and one of said inter-chip ground electrodes is aligned in a first direction and is sandwiched between a pair of inter-chip signal electrodes, which are immediately adjacent each other and aligned in a second direction crossing said first direction,
wherein current flowing through said inter-chip power source electrode is opposite in direction to current flowing through said inter-chip ground electrode.
4. The semiconductor device according to claim 1 , wherein said semiconductor chips include an interface chip and a plurality of DRAM chips consecutively disposed on said interface chip, and said DRAM chips are connected to an external circuit via said interface chip.
5. The semiconductor device according to claim 2 , wherein said two electrode pairs are aligned in a first direction and further comprising a third electrode pair including one of said inter-chip power source electrodes and one of said inter-chip ground electrodes, said third electrode pair being aligned in a second direction that is perpendicular to said first direction.
6. The semiconductor device according to claim 3 , wherein said second direction is perpendicular to said first direction.