Semiconductor memory device with stable internal power supply voltage
View Patent ↗A semiconductor memory device having a register for stably generating an internal power supply voltage, including: a pumping circuit unit for generating the internal power supply voltage and adjusting a voltage level of the internal power supply voltage in response to a control signal; and a decoding unit for generating the control signal based on a plurality of address signals of the register.
1. A semiconductor memory device having a register for stably generating an internal power supply voltage, comprising:
a pumping circuit unit including a plurality of pumping circuits which are selectively operated based on a control signal and generating the internal power supply voltage and adjusting a voltage level of the internal power supply voltage in response to the control signal; and
a decoding unit for generating the control signal based on a plurality of address signals of the register,
wherein the register is a mode register set (MRS) or an extended mode register set (EMRS), and a first address signal of the plurality of address signals determines whether or not the plurality of pumping circuits are selectively operated.
2. The semiconductor memory device as recited in claim 1 , wherein a second address signal to a fifth address signal of the plurality of address signals determine the number of pumping circuits to be operated.
3. The semiconductor memory device as recited in claim 2 , wherein the internal power supply voltage is an internal low power supply voltage having lower voltage level than the external power supply voltage.
4. The semiconductor memory device as recited in claim 2 , wherein the internal power supply voltage is an internal high power supply voltage having higher voltage level than the external power supply voltage.
5. A semiconductor memory device for stably generating an internal power supply voltage, comprising:
a pumping circuit unit for generating the internal power supply voltage and adjusting a voltage level of the internal power supply voltage at a test mode in response to a control signal; and
a decoding unit for generating the control signal in order to operate the pumping circuit unit at a normal mode or the test mode in response to a plurality of control signals,
wherein the test mode or the normal mode is determined by a mode register set (MRS) or an extended mode register set (EMRS), and the plurality of control signals are plurality of address signals of the MRS or the EMRS.
6. The semiconductor memory device as recited in claim 5 , wherein the pumping circuit unit includes a plurality of pumping circuits and the plurality of pumping circuits are selectively operated at the test mode, and all of the plurality of pumping circuits are operated at the normal mode.
7. The semiconductor memory device as recited in claim 6 , wherein a first address signal of the plurality of address signals selects one of the test mode and the normal mode.
8. The semiconductor memory device as recited in claim 7 , wherein a second address signal to a fifth address signal of the plurality of address signals determine the number of pumping circuits to be operated.
9. A semiconductor memory device, comprising:
a register for outputting a plurality of address signals;
a decoding unit for generating a control signal based on the plurality of address signals; and
a plurality of pumping circuits for generating an internal power supply voltage and adjusting a voltage level of the internal power supply voltage in response to the control signal,
wherein a first address signal of the plurality of address signals determines whether the plurality of pumping circuits are selectively operated or not.
10. The semiconductor memory device as recited in claim 9 , wherein the register is a mode register set (MRS) or an extended mode register set (EMRS).
11. The semiconductor memory device as recited in claim 10 , wherein the plurality of pumping circuits are selectively operated based on the control signal.
12. The semiconductor memory device as recited in claim 11 , wherein a second address signal to a fifth address signal of the plurality of address signals determine the number of pumping circuits to be operated.
13. The semiconductor memory device as recited in claim 12 , wherein the internal power supply voltage is an internal low power supply voltage having lower voltage level than the external power supply voltage.
14. The semiconductor memory device as recited in claim 12 , wherein the internal power supply voltage is an internal high power supply voltage having higher voltage level than the external power supply voltage.