Method of manufacturing CMOS transistor by using SOI substrate
View Patent ↗In a method of manufacturing a CMOS transistor, an n-channel MOS transistor is formed on an upper MOS transistor in a first region of an SOI substrate having first and second regions. Next, an insulating layer of the SOI substrate is exposed by removing an upper silicon layer in a second region, and then, a first insulating layer is formed to cover the first and second regions. Next, a silicon epitaxial layer is formed on the first insulating layer of the second region, and then, a p-channel MOS transistor is formed on the silicon epitaxial layer. An n-channel MOS transistor is formed on the upper silicon layer of the SOI substrate and a p-channel MOS transistor on the first insulating layer has a vertical step (relative to the n-channel MOS transistor), so that it is possible to increase integration degree.
1. A method of manufacturing a CMOS transistor, comprising steps of:
preparing a SOI substrate having
an insulating layer between lower and upper silicon layers,
a first region where an n-channel MOS transistor is to be formed, and
a second region where a p-channel MOS transistor is to be formed;
subsequently forming a first gate insulating layer pattern and a first gate conductive layer pattern on the upper silicon layer of the first region in the SOI substrate;
forming a first source/drain region on the upper silicon layer of the first region by performing a first ion implanting process;
removing the upper silicon layer of the second region, including using a mask film pattern for covering the first region as an etching mask;
forming a first insulating layer on the upper silicon layer and the first gate conductive layer pattern of the first region and the insulating layer exposed in the second region;
forming a second insulating layer on the first insulating layer;
exposing a portion of a surface of the first insulating layer in the second region by removing a portion of the second insulating layer;
forming a silicon epitaxial layer on the surface of the first insulating layer exposed in said exposing step and removing the second insulating layer;
forming a second gate insulating layer pattern and a second gate conductive layer pattern on the silicon epitaxial layer; and
forming second source/drain regions on the silicon epitaxial layer by performing a second ion implanting process.
2. The method of claim 1 , wherein the step of forming a first insulating layer includes forming a low temperature oxide layer having a thickness in an inclusive range of 1000 through 5000 Å.
3. The method of claim 2 , wherein, after the low temperature oxide layer is formed, a top surface of the low temperature layer is planarized by performing a planarization process.
4. The method of claim 1 , wherein the step of forming the silicon epitaxial layer includes forming the silicon epitaxial layer to have a thickness of 1000 through 5000 Å.
5. The method of claim 1 , wherein the step of forming the second insulating layer includes forming a low temperature oxide layer having a thickness in an inclusive range of 1000 through 5000 Å.
6. The method of claim 1 , wherein the first ion implanting process is performed by implanting arsenic (As) ions with an implanting energy of about 5 to 50 keV and a concentration of about 5×10 14 to 1×10 15 ions/cm 2 .
7. The method of claim 1 , wherein the second ion implanting process is performed by implanting boron (B) ions with an implanting energy of about 2 to 50 keV and a concentration of about 5×10 14 to 5×10 15 ions/cm 2 .
8. A method of manufacturing a CMOS transistor comprises steps for:
preparing a SOI substrate having
an insulating layer between lower and upper silicon layers,
a first region where an n-channel MOS transistor is to be formed, and
a second region where a p-channel MOS transistor is to be formed;
subsequently forming a first gate insulating layer pattern and a first gate conductive layer pattern on the upper silicon layer of the first region in the SOI substrate;
forming a first source/drain region on the upper silicon layer of the first region by performing a first ion implanting process;
removing the upper silicon layer of the second region, including using a mask film pattern for covering the first region as an etching mask;
forming a first insulating layer on the upper silicon layer and the first gate conductive layer pattern of the first region and the insulating layer exposed in the second region;
forming a second insulating layer on the first insulating layer;
exposing a portion of a surface of the first insulating layer in the second region by removing a portion of the second insulating layer;
forming a silicon epitaxial layer on the surface of the first insulating layer exposed in said exposing step and removing the second insulating layer;
forming a second gate insulating layer pattern and a second gate conductive layer pattern on the silicon epitaxial layer; and
forming second source/drain regions on the silicon epitaxial layer by performing a second ion implanting process.