Semiconductor device and method for fabricating the same
View Patent ↗A transistor and a method for fabricating the same is disclosed, to uniformly provide impurity ions in impurity areas, and to prevent a short channel effect, in which the method for fabricating the transistor includes steps of forming a plurality of channel ion implantation areas having different depths in a first conductive type semiconductor substrate; forming a pillar by selectively etching the first conductive type semiconductor substrate; sequentially depositing a gate insulating layer and a conductive layer for a gate electrode on the first conductive type semiconductor substrate including the pillar; forming the gate electrode by selectively patterning the conductive layer; and forming second conductive type source/drain impurity ion areas in the first conductive type semiconductor substrate corresponding to the top of the pillar and both sidewalls of the pillar.
1. A method for fabricating a semiconductor device comprising:
forming a pillar by selectively etching a first conductive type semiconductor substrate;
forming first conductive type halo-ion areas in the surface of the first conductive type semiconductor substrate corresponding to the pillar and sides of the pillar;
forming second conductive type impurity ion areas on the halo-ion areas;
after forming the first conductive type halo-ion areas and the second conductive type impurity ion areas, depositing a gate insulating layer and a conductive layer for a gate electrode on an entire surface of the first conductive type semiconductor substrate including the pillar;
forming the gate electrode by selectively patterning the gate insulating layer and the conductive layer; and
forming a spacer at a sidewall of the gate electrode.
2. The method of claim 1 , further comprising:
forming an insulating interlayer on the entire surface of the first conductive type semiconductor substrate including the gate electrode;
forming contact holes in the insulating interlayer to expose predetermined portions of the second conductive type impurity ions areas and the gate electrode; and
forming electrodes for being electrically connected with the second conductive type impurity ion areas and the gate electrode by the contact holes.
3. The method of claim 1 , wherein the halo-ions areas arc formed by implanting the first conductive type impurity ions at an energy between 5 KeV and 50 KeV and a density between 1E14 and 5E14 ions/cm 2 .
4. The method of claim 1 , wherein the first conductive type halo-ion areas are formed by implanting halo-type ions at an angle of from 5° to 30° relative to a vertical axis of the surface of the first conductive type semiconductor substrate.
5. A method for fabricating a semiconductor device comprising:
forming a sacrificial oxide layer on a first conductive type semiconductor substrate;
forming an aperture in the sacrificial oxide layer to expose a predetermined portion of the first conductive type semiconductor substrate;
forming a polysilicon layer in the aperture;
removing the sacrificial oxide layer;
forming first conductive type halo-ion areas in the polysilicon layer and the first conductive type semiconductor substrate at sides of the polysilicon layer;
forming second conductive type impurity ion areas on the halo-ion areas at sides of the polysilicon layer;
sequentially depositing a gate insulating layer and a conductive layer for a gate electrode on an entire surface of the first conductive type semiconductor substrate including the polysilicon layer;
forming a gate electrode by selectively patterning the gate insulating layer and the conductive layer; and
forming a spacer at a sidewall of the gate electrode.
6. The method of claim 5 , further comprising:
forming an insulating interlayer on the entire surface of the first conductive type semiconductor substrate including the gate electrode;
forming contact holes in the insulating interlayer to expose predetermined portions of the second conductive type impurity ions areas and the gate electrode; and
forming electrodes for being electrically connected wit the second conductive type impurity ions areas and the gate electrode by the contact holes.
7. The method of claim 5 , wherein the halo-ion areas are formed by implanting first conductive impurity ions at an energy between 5 KeV and 50 KeV and a density between 1E14 and 5E14 ions/cm 2 .
8. The method of claim 5 , wherein the halo-ion areas are formed by implanting halo-type ions at an angle of from 5° to 30° relative to a vertical axis of the surface of the substrate.
9. The method of claim 5 , wherein the sacrificial oxide layer has a thickness of from 1000 Å to 5000 Å.
10. The method of claim 1 , wherein selectively patterning the gate insulating layer and the conductive layer comprises leaving unetched portions of the gate insulating layer and the conductive layer over a top surface of the pillar, side surfaces of the pillar, and horizontal areas of the substrate adjacent to the pillar.
11. The method of claim 2 , wherein forming second conductive type impurity ion areas comprises forming a drain region over the halo ion area within the pillar, and forming a source region above the halo ion area within the substrate adjacent to the pillar.
12. The method of claim 11 , wherein forming electrodes comprises forming a second gate electrode electrically connected with the gate electrode, a source electrode electrically connected with the source region, and a drain electrode electrically connected with the drain region.
13. The method of claim 1 , wherein forming second conductive type impurity ion areas comprises implanting impurity ions at an, energy between 5 KeV and 50 KeV and a density between 1E14 and 5E14 ions/cm 2 .
14. The method of claim 1 , wherein selectively etching a first conductive type semiconductor substrate comprises removing portions of the substrate adjacent to the pillar having a thickness of about 1 μm to 2 μm.
15. The method of claim 1 , further comprising forming a buffering oxide layer prior to forming a pillar.
16. The method of claim 1 , wherein forming the spacer comprises:
forming an insulating layer comprising an oxide layer and a nitride layer, and having a thickness between about 600 Å and 2000 Å; and
etching back the insulating layer until horizontal surfaces of the gate electrode are exposed.
17. The method of claim 5 , wherein selectively patterning the gate insulating layer and the conductive layer comprises leaving unetched portions of the gate insulating layer and the conductive layer over a top surface of the pillar, side surfaces of the pillar, and adjacent horizontal areas of the substrate.
18. The method of claim 6 , wherein forming second conductive type impurity ion areas comprises forming a drain region over the halo ion area within the pillar, and forming a source region above the halo ion area within the substrate adjacent to the pillar.
19. The method of claim 18 , wherein forming electrodes comprises forming a second gate electrode electrically connected with the gate electrode, a source electrode electrically connected with the source region, and a drain electrode electrically connected with the drain region.
20. The method of claim 5 , wherein forming the polysilicon layer in the aperture comprises epitaxially growing polysilicon to a thickness between about 0.5 μm and 3 μm.