Method of programming, reading and erasing memory-diode in a memory-diode array
A memory array includes first and second sets of conductors and a plurality of memory-diodes, each connecting in a forward direction a conductor of the first set with a conductor of the second set. An electrical potential is applied across a selected memory-diode, from higher to lower potential in the forward direction, intended to program the selected memory-diode. During this intended programming, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage. The threshold voltage of each memory-diode can be established by applying an electrical potential across that memory-diode from higher to lower potential in the reverse direction. By so establishing a sufficient threshold voltage, and by selecting appropriate electrical potentials applied to conductors of the array, problems related to current leakage and disturb are avoided.
1. A method of providing a state of a memory-diode comprising:
applying a first electrical potential across the memory-diode to provide a memory-diode conductive state; and
applying a second electrical potential across the memory-diode to establish a memory-diode threshold voltage for the memory-diode in its conductive state, beyond which the memory-diode remains in its conductive state.
2. The method of claim 1 wherein the first electrical potential is applied from higher to lower electrical potential in the forward direction of the memory-diode.
3. The method of claim 2 wherein the second electrical potential is applied from higher to lower electrical potential in the reverse direction of the memory-diode.
4. The method of claim 1 wherein the second electrical potential is applied from higher to lower electrical potential in the reverse direction of the memory-diode.
5. The method of claim 1 and further comprising applying a third electrical potential across the memory-diode from higher to lower electrical potential in the reverse direction of the memory-diode, the third electrical potential being greater than the second electrical potential.
6. The method of claim 4 and further comprising applying a third electrical potential across the memory-diode from higher to lower electrical potential in the reverse direction of the memory-diode, the third electrical potential being greater than the second electrical potential.
7. The method of claim 6 wherein the step of applying a third electrical potential across the memory-diode from higher to lower electrical potential in the reverse direction of the memory-diode is a memory diode erase step.
8. A method of establishing a threshold voltage of a conductive memory-diode beyond which the memory-diode remains in its conductive state, comprising applying an electrical potential across the memory-diode, from higher to lower electrical potential in the reverse direction of the memory-diode.
9. The method of claim 8 wherein the established threshold voltage of the memory-diode is dependent on the magnitude of the electrical potential applied across the memory-diode, from higher to lower electrical potential in the reverse direction of the memory-diode.
10. The method of claim 9 wherein the established threshold voltage of the memory-diode increases with increase in the magnitude of the electrical potential applied across the memory-diode, from higher to lower electrical potential in the reverse direction of the memory-diode.
11. A method of undertaking a procedure on a memory-diode comprising:
providing an electrical potential across the memory-diode from higher to lower electrical potential in the reverse direction of the memory-diode, to provide an erase state of the memory-diode; and
applying an electrical potential across the memory-diode from higher to lower electrical potential in the forward direction of the memory-diode to verify the state of the memory diode.
12. The method of claim 11 wherein the step of applying an electrical potential across the memory-diode from higher to lower electrical potential in the forward direction of the memory diode is a memory diode read step.
13. A method of undertaking a procedure on a memory-diode which is in a conductive state, comprising:
applying an electrical potential across the memory-diode from higher to lower electrical potential in the forward direction of the memory-diode, to read the state of the memory-diode; and
applying an electrical potential across the memory-diode from higher to lower electrical potential in the reverse direction of the memory-diode to establish a memory-diode threshold voltage.
14. The method of claim 13 wherein the procedure undertaken on the memory-diode is a read-completion procedure.
15. A method of undertaking a procedure on a selected memory-diode of a memory array, said memory array comprising a first plurality of conductors, a second plurality of conductors, and a plurality of memory-diodes, each connecting a conductor of the first plurality thereof with a conductor of the second plurality thereof, comprising;
providing an electrical potential across the selected memory-diode, from higher to lower electrical potential in the forward direction of the selected memory-diode, to program the selected memory-diode to a conductive state; and
providing that, during the programming of the selected memory-diode, each other programmed memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage.
16. The method of claim 15 and further comprising the step of, after programming the selected memory-diode to a conductive state, applying an electrical potential across the selected memory-diode, from higher to lower electrical potential in the reverse direction of the selected memory-diode, to determine a threshold voltage of the selected memory-diode.
17. The method of claim 16 and further comprising providing that, during the programming of the selected memory-diode, each other memory-diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage.
18. A method of erasing a selected programmed memory-diode of a memory array, said memory array comprising a first plurality of conductors, a second plurality of conductors crossing the first plurality of conductors, and a plurality of memory-diodes, each connecting a conductor of the first plurality thereof with a conductor of the second plurality thereof, comprising;
providing an electrical potential across the selected memory-diode, from higher to lower potential in the reverse direction of the selected memory-diode, to erase the selected memory-diode and provide an erase state thereof; and
providing that, during the erasing of the selected memory-diode, each other programmed memory-diode in the array has provided thereacross in the reverse direction thereof an electrical potential lower than the electrical potential provided to erase the selected memory-diode.
19. The method of claim 18 and further comprising providing that, during the erasing of the selected memory-diode, each other memory-diode in the array has provided thereacross in the reverse direction thereof an electrical potential lower than the electrical potential provided to erase the selected memory-diode.
20. The method of claims 18 and further comprising, after undertaking the erase of the selected memory-diode, applying an electrical potential across the selected memory-diode from higher to lower electrical potential in the forward direction of the selected memory-diode to verify the state of the selected memory diode.
21. The method of claim 20 wherein the step of applying an electrical potential across the selected memory-diode from higher to lower electrical potential in the forward direction of the selected memory-diode is a memory-diode read step.
22. A method of undertaking a procedure on a selected memory-diode of a memory array, said memory array comprising a first plurality of parallel conductors, a second plurality of parallel conductors orthogonal to and crossing the first plurality of conductors, and a plurality of memory-diodes, each connecting a conductor of the first plurality thereof with a conductor of the second plurality thereof, comprising;
providing an electrical potential across the selected memory-diode, from higher to lower potential in the forward direction of the selected memory-diode, to program the selected memory-diode to a conductive state;
providing that, during the programming of the selected memory diode, each other memory diode in the array has provided thereacross in the forward direction thereof an electrical potential lower than its threshold voltage;
providing an electrical potential across the selected memory-diode, from higher to lower potential in the reverse direction of the selected memory-diode, to erase the selected memory-diode and provide an erase state thereof; and
providing that, during the erasing of the selected memory-diode, each other memory-diode in the array has provided thereacross in the reverse direction thereof an electrical potential lower than the electrical potential provided to erase the selected memory-diode.
23. The method of claim 22 and further comprising the step of, after programming the selected memory-diode to a conductive state and prior to erasing the selected memory-diode, applying an electrical potential across the selected memory-diode, from higher to lower electrical potential in the reverse direction of the selected memory-diode, to determine a threshold voltage of the selected memory-diode.
24. The method of claim 22 and further comprising the step of, after programming the selected memory-diode to a conductive state and prior to erasing the selected memory-diode,
applying an electrical potential across the programmed selected memory-diode from higher to lower electrical potential in the forward direction of the selected memory-diode, to read the state of the selected memory-diode; and
applying an electrical potential across the selected memory-diode from higher to lower electrical potential in the reverse direction of the memory-diode to establish a threshold voltage of the selected memory-diode.
25. The method of claim 22 and further comprising the step of, after undertaking the erase of the selected memory-diode, applying an electrical potential across the selected memory-diode from higher to lower electrical potential in the forward direction of the selected memory-diode to verify the state of the memory-diode.
26. The method of claim 25 wherein the step of applying an electrical potential across the selected memory-diode from higher to lower electrical potential in the forward direction of the selected memory-diode is a memory diode-read step.