IP Library Granted Patent US 7,246,026
Granted Patent B2
US 7,246,026 · App. 11/022,148 · Granted Jul 17, 2007

Multi-domain execution of tests on electronic devices

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Quick Facts
Patent No.
US 7,246,026
App. No.
11/022,148
Granted
Jul 17, 2007
Kind
B2
Abstract

A device under test is divided into multiple test domains, and test conditions for each of the multiple test domains are defined separately, so that each test domain has its own test pattern, timing data, and other test conditions. Each test domain can start and stop independently, and run at different speeds. Further, triggers are used to specify how the tests executed in the different test domains interact and communicate with one another. Any test domain can generate or wait for a trigger from any other test domain (including the CPU).

Claims (42)

1. A method of testing an electronic device, comprising:

(a) designating multiple test domains for the electronic device;

(b) defining a test for each of the multiple test domains separately, each such definition specifying a test pattern and timing data to be used with the test;

(c) defining triggers for initiating each test defined in (b);

(d) executing the tests and triggers defined in (b) and (c); wherein the test and the triggers are defined as extensible markup language (XML) blocks and passed as objects during (d); and

(e) storing test and trigger results operable for access by a user.

2. The method according to claim 1 , wherein the tests defined for at least two of the test domains specify tests carried out at different speeds.

3. The method according to claim 1 , wherein the electronic device is a mixed signal device and one of the test domains is an analog test domain and another of the test domains is a digital test domain.

4. The method according to claim 3 , wherein said tests defined for at least two of the test domains specify tests carried out at different speeds.

5. A computer-readable medium having stored therein program instructions to execute a method for testing an electronic device comprising:

(a) initiating a test for a first test region of the electronic device at a first test instrument of said apparatus;

(b) generating a trigger at the first test instrument in response to an event associated with the first test region of the electronic device;

(c) initiating a test for a second test region of the electronic device at a second test instrument of said apparatus in response to a receipt of the trigger at the second test instrument,

wherein the program instructions comprise extensible markup language (XML) blocks, each of the XML blocks corresponding to a test for one test region and specifying a test pattern and timing data to be used with the test for said test region; and

(d) storing test and trigger results operable for access by a user.

6. The computer-readable medium according to claim 5 , wherein the program instructions define the test from the first test region separately for the test for the second test region, each such test definition specifying a test pattern and timing data to be used with the test.

7. The computer-readable medium according to claim 5 , wherein the program instructions further comprise XML blocks that define triggers.

8. The computer-readable medium according to claim 5 , wherein said initiating comprises executing a test pattern to generate test signals to be supplied to the first region of the electronic device.

9. A computer-readable medium according to claim 8 , wherein the event associated with the first test region comprises a programmed event in the test pattern.

10. A computer-readable medium according to claim 8 , wherein the event associated with the first test region comprises an event detected in outputs of the first test region of the electronic device generated in response to the test signals supplied to the first test region of the electronic device.

11. The computer-readable medium according to claim 5 , wherein the test for the first test region is carried out at a first clock speed and the test for the second test region is carried out at a second clock speed that is different from the first clock speed.

12. A computer-readable medium having stored therein program instructions to be executed in an apparatus for testing an electronic device, said method comprising:

(a) designating multiple test domains for the electronic device;

(b) defining a test for each of the multiple test domains separately, each such definition specifying a test pattern and timing data to be used with the test;

(c) defining triggers for initiating each test defined in (b);

(d) executing the tests and triggers defined in (b) and (c), wherein the test and the triggers are defined as extensible markup language (XML) blocks and passed as objects during (d); and

(e) storing test and trigger results operable for access by a user.

13. The computer-readable medium as described in claim 12 , wherein the tests defined for at least two of the test domains specify tests carried out at different speeds.

14. The computer-readable medium as described in claim 12 , wherein the electronic device is a mixed signal device and one of the test domains is an analog test domain and another of the test domains is a digital test domain.

15. The computer-readable medium as described in claim 14 , wherein said tests defined for at least two of the test domains specify tests carried out at different speeds.

16. A method for testing an electronic device, wherein said method comprising:

(a) initiating a test for a first test region of the electronic device at a first test instrument of said apparatus;

(b) generating a trigger at the first test instrument in response to an event associated with the first test region of the electronic device;

(c) initiating a test for a second test region of the electronic device at a second test instrument of said apparatus in response to a receipt of the trigger at the second test instrument,

wherein the program instructions comprise extensible markup language (XML) blocks, each of the XML blocks corresponding to a test for one test region and specifying a test pattern and timing data to be used with the test for said test region; and

(d) storing test and trigger results operable for access by a user.

17. The method as described in claim 16 , wherein the program instructions define the test from the first test region separately for the test for the second test region, each such test definition specifying a test pattern and timing data to be used with the test.

18. The method as described in claim 16 , wherein the program instructions further comprise XML blocks that define triggers.

19. The method as described in claim 16 , wherein said initiating comprises executing a test pattern to generate test signals to be supplied to the first region of the electronic device.

20. The method as described in claim 19 , wherein the event associated with the first test region comprises a programmed event in the test pattern.

21. The method as described in claim 19 , wherein the event associated with the first test region comprises an event detected in outputs of the first test region of the electronic device generated in response to the test signals supplied to the first test region of the electronic device.

22. The method as described in claim 16 , wherein the test for the first test region is carried out at a first clock speed and the test for the second test region is carried out at a second clock speed that is different from the first clock speed.

Assignments (8)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS, RECORDED AT REEL 047185, FRAME 0624 Recorded Mar 7, 2024
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS AGENT
To: XCERRA CORPORATION
Reel/Frame 066762/0811 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT STATEMENT THAT THIS DOCUMENT SERVES AS AN OATH/DECLARATION PREVIOUSLY RECORDED ON REEL 047185 FRAME 0628. ASSIGNOR(S) HEREBY CONFIRMS THE PATENT SECURITY AGREEMENT. Recorded Nov 28, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047675/0354 →
PATENT SECURITY AGREEMENT Recorded Oct 2, 2018
From: XCERRA CORPORATION
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 047185/0624 →
CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 7261561 AND REPLACE WITH PATENT NUMBER 7231561 PREVIOUSLY RECORDED ON REEL 034660 FRAME 0188. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY AGREEMENT. Recorded Feb 11, 2016
From: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 037824/0372 →
SECURITY AGREEMENT Recorded Dec 18, 2014
From: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 034660/0188 →
RELEASE OF SECURITY INTEREST IN UNITED STATES PATENTS Recorded Dec 18, 2014
From: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
To: XCERRA CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
Reel/Frame 034660/0394 →
CHANGE OF NAME Recorded May 27, 2014
From: LTX-CREDENCE CORPORATION
To: XCERRA CORPORATION
Reel/Frame 033032/0768 →
SECURITY AGREEMENT Recorded Jan 17, 2014
From: LTX-CREDENCE CORPORATION; EVERETT CHARLES TECHNOLOGIES LLC
To: SILICON VALLEY BANK, AS ADMINISTRATIVE AGENT
Reel/Frame 032086/0476 →