IP Library Patent Application 11022460
Patent Application
App. No. 11/022,460

Method of forming dielectric layer in semiconductor device

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Patent No.
US None
App. No.
11/022,460
Abstract

A method of forming an insulating film of a semiconductor device is disclosed. Where an insulating film is formed and an annealing process is then performed to remove out-gassing sources contained in the insulating film. Spot-shaped defects and by-products or CH-radicals, which are formed on the surface of the insulating film, are then removed by thermal treatment. The generation of such defects on the surface of the insulating film is therefore minimized and potential failures such as broken or thin patterns formed on the insulating film are avoided. Accordingly, the reliability of the manufacturing process and the electrical properties of resulting devices are improved.

Claims (17)

1 . A method of forming an insulating film in a semiconductor device, comprising:

forming an interlayer insulating film on a semiconductor substrate; and

performing thermal treatment to remove out-gassing sources contained in the interlayer insulating film.

2 . The method as claimed in claim 1 , wherein the interlayer insulating film is composed of any one of LP_TEOS, BPSG and SOD.

3 . The method as claimed in claim 1 , wherein the thermal treatment is performed in a rapid thermal processing (RTP) mode in a gas atmosphere of O 2 , a gas atmosphere of N 2 O or in a vacuum state.

4 . The method as claimed in claim 3 , wherein the RTP is performed at a temperature ranging from 700° C. to 1000° C. for 20 to 100 seconds.

5 . The method as claimed in claim 3 , wherein the thermal treatment is performed in a furnace in a gas atmosphere of O 2 , a gas atmosphere of N 2 O or in a vacuum state.

6 . The method as claimed in claim 5 , wherein the thermal treatment is performed at a temperature ranging from 700° C. to 1000° C. for 30 minutes to 1 hour.

7 . The method as claimed in claim 1 , further comprising, after the thermal treatment is performed, applying a surface treatment to the interlayer insulating film in order to further remove out-gassing sources or by-products adsorbed on the surface of the interlayer insulating film, or spot defects formed on the surface of the interlayer insulating film.

8 . The method as claimed in claim 7 , wherein the surface treatment is performed in an oxygen plasma treatment mode, a plasma etch-back mode, a wet etch-back mode or a chemical-mechanical polishing mode.

9 . The method as claimed in claim 8 , wherein the surface treatment of the oxygen plasma treatment mode is performed for 10 to 60 seconds while applying the plasma power of 200 to 1000 W and supplying O 2 of 300 to 700 sccm.

10 . The method as claimed in claim 8 , wherein the surface treatment of the plasma etch-back mode is performed using a C x F y -based or NF-based fluorine-containing gas for 10 to 50 seconds while applying a bias of 300 to 500 W at a pressure of 10 mTorr to 50 mTorr.

11 . The method as claimed in claim 10 , wherein the fluorine-containing gas employs one of CHF 3 , CF 4 and C 3 F 8 , or a mixture of any two thereof.

12 . The method as claimed in claim 11 , wherein the flow rate of the fluorine-containing gas is set to 10 to 200 sccm.

13 . The method as claimed in claim 7 , wherein the surface treatment of the wet etch mode is performed using an NH 4 F-based or NF-based fluorine-containing solution as an etchant at a temperature ranging from room temperature to 70° C. for 1 to 10 minutes.

14 . The method as claimed in claim 13 , wherein the fluorine-containing solution employs a DHF solution in which H 2 O and HF are mixed in the ratio of 50:1 to 200:1, or a BOE solution in which NH 4 F and DHF are mixed in the ratio of 100:1 to 300:1.

15 . The method as claimed in claim 7 , wherein in the surface treatment of a CMP mode, a target polishing thickness is set to below 100 Å and the CMP mode uses a CMP slurry that is a silica-based slurry.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 6, 2006
From: HYNIX SEMICONDUCTOR INC.
To: HYNIX SEMICONDUCTOR INC.; STMICROELECTRONICS S.R.L.
Reel/Frame 018207/0057 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2004
From: KIM, JUNG GEUN
To: HYNIX SEMICONDUCTOR INC.
Reel/Frame 016130/0601 →