Method of fabricating self-aligned bipolar transistor
View Patent ↗The present invention provides a method of fabricating a self-aligned bipolar transistor, by which the fabricating method can be simplified by forming P+ and N+ junctions by self-alignment and by which device reliability can be enhanced. The present invention includes the steps of forming a well in a substrate isolated by a device isolation layer, forming a polysilicon gate on the substrate, forming an insulating layer on the substrate, forming a sidewall spacer on lateral sides of the polysilicon gate by etching the insulating layer, forming a P + ion implanted region in the substrate, forming an N + ion implanted region in the substrate, and forming silicide on the P + and N + ion implanted regions.
1. A method of fabricating a self-aligned bipolar transistor, comprising the steps of:
forming at least one trench in a portion of a first conductive type substrate;
filling the at least one trench with an isolating material to form a device isolation layer;
forming a second conductive type well in the substrate isolated by the device isolation layer, the second conductive type being different from the first conductive type;
forming a polysilicon gate on the substrate;
forming an insulating layer on the substrate;
forming a sidewall spacer on lateral sides of the polysilicon gate by etching the insulating layer;
forming a P + ion implanted region in a first portion of the second conductive type well;
forming an N + ion implanted region in a second portion of the second conductive type well, the second portion being separated from the first portion; and
forming a silicide layer in contact with the P + and N + ion implanted regions.
2. The method of claim 1 , wherein the sidewall spacer is formed by performing anisotropic etch on the insulating layer.
3. The method of claim 1 , wherein each of the P + and N + ion implanted regions is formed by ion implantation using the polysilicon gate and the sidewall spacer as an ion implantation mask.