Method for fabricating an NROM memory cell array
View Patent ↗In the method, trenches are etched and, in between, bit lines ( 8 ) are in each case arranged on doped source/drain regions ( 3, 4 ). Storage layers ( 5, 6, 7 ) are applied and gate electrodes ( 2 ) are arranged at the trench walls. After the introduction of polysilicon, which is provided for the gate electrodes ( 2 ), into the trenches, the top side is ground back in a planarizing manner until the top side of the covering layer ( 16 ) is reached, and afterward a polysilicon layer ( 18 ), which is provided for the word lines, is applied over the whole area and patterned to form the word lines.
1. A method for fabricating an NROM memory cell array, the method comprising:
introducing dopant at a top side of a semiconductor body, in order to form source/drain regions;
etching trenches arranged parallel at a distance from one another into the semiconductor body;
forming bit lines running parallel to the trenches and arranged between adjacent ones of said trenches on the top side of the semiconductor body, each bit line being electrically conductively connected to source/drain regions located between the adjacent ones of the trenches;
forming supporting structures outside a memory cell array region, the supporting structures being formed concurrently with the bit lines;
applying a covering layer on the top side of the bit lines;
applying a storage layer to the walls of the trenches;
filling the trenches with conductive gate electrode material;
after filling the trenches, removing the top side of said conductive gate electrode material in a planarizing manner until a top side of the covering layer is reached, wherein the supporting structures serve to support the planarizing outside the memory cell array region;
after removing the material, depositing conductive word line material; and
patterning the conductive word line material to form word lines that run transversely with respect to the direction of the bit lines, the word lines being electrically conductively coupled to gate electrode disposed within the trenches.
2. The method as claimed in claim 1 , wherein removal of the material is performed by means of chemical mechanical polish (CMP).
3. The method as claimed in claim 2 , wherein applying a covering layer comprising forming a nitride or oxide layer over the bit lines.
4. The method as claimed in claim 3 , wherein the covering layer is used as a stop layer during the removal of the conductive gate electrode material.
5. The method as claimed in claim 4 wherein the conductive gate electrode material comprises polysilicon.
6. The method as claimed in claim 1 , wherein applying a covering layer comprising forming a nitride or oxide layer over the bit lines.
7. The method as claimed in claim 6 , wherein the covering layer is used as a stop layer during the removal of the conductive gate electrode material.
8. The method as claimed in claim 7 , wherein the conductive gate electrode material comprises polysilicon.
9. The method as claimed in claim 1 , wherein the conductive gate electrode material comprises polysilicon.
10. The method as claimed in claim 9 , wherein the conductive word line material comprises polysilicon.
11. A method for fabricating a memory cell in an active region, the method comprising:
patterning at least one film of an electrically conductive layer to form strip-like sections on a semiconductor material;
forming at least one support structure outside of said active region on said semiconductor material, said at least one support structure being formed concurrently with the forming of said strip like sections;
forming a doped region for a source and a doped region for a drain;
forming a trench having sides between the strip-like sections of the electrically conductive layer such that the doped region for the source remains at one of the sides of the trench and the doped region for the drain remains at another one of the sides of the trench;
applying a boundary layer, a memory layer arid a boundary layer on top of one another over an entire surface of the semiconductor material;
introducing an electrically conductive material for a gate electrode into the trench;
planarizing an upper surface of the electrically conductive material, wherein said at least one structure serves to support the step of planarizing; and
forming electrically conductive word lines over the planarized upper surface.
12. The method of claim 11 wherein the semiconductor material comprises a semiconductor layer.
13. The method of claim 11 wherein forming a doped region for a source and a doped region for a drain comprises performing an implantation.
14. The method of claim 11 wherein forming a doped region for a source and a doped region for a drain comprises diffusing dopant out of a material of the electrically conductive layer.
15. The method of claim 11 , wherein the electrically conductive material comprises polysilicon.
16. The method of claim 15 , wherein forming word lines comprises depositing and patterning polysilicon.
17. The method of claim 11 wherein the planarizing step comprises performing a chemical mechanical polish (CMP).
18. The method of claim 11 and further comprising forming a covering layer over the electrically conductive film, the covering layer being formed into strip-like sections along with the electrically conductive film.
19. The method of claim 18 wherein the covering layer is used as a mask during the forming of a trench.