Self-aligned element isolation film structure in a flash cell and forming method thereof
View Patent ↗A self-aligned element isolation film structure in a flash memory cell and a forming method thereof are disclosed. An example method of forming a self-aligned element isolation film structure in a flash memory cell forms an insulating layer on a semiconductor substrate and forms a floating gate pattern on the insulating layer. The example method selectively implants ions in a portion of the insulating layer exposed by the floating gate pattern and forms a self-aligned element isolation film on the floating gate pattern by oxidizing and growing the portion of the insulating layer to which the ion implantation is performed.
1. A method of forming a self-aligned element isolation film structure in a flash memory cell, the method comprising:
forming an insulating layer on a semiconductor substrate;
forming a floating gate pattern on the insulating layer;
selectively implanting ions in a portion of the insulating layer which is exposed by the floating gate pattern; and
forming a self-aligned element isolation film on the floating gate pattern by oxidizing and growing the portion of the insulating layer to which the ion implantation is performed.
2. The method of claim 1 , wherein forming the floating gate pattern comprises forming a photo resist pattern in which an element isolation region is exposed, on the floating gate layer and selectively etching the exposed portion of the floating gate layer using the photo resist pattern as an etching mask to expose the surface of the insulating layer.
3. The method of forming of claim 1 , further comprising heating the insulating layer after the ions have been selectively implanted therein.
4. The method of claim 1 , wherein the floating gate pattern comprises a polysilicon film, and the polysilicon film is used as an ion implantation mask for shielding a portion of the insulating layer under the floating gate pattern at the time of selectively implanting the ions.
5. The method of claim 1 , wherein the self-aligned element isolation film is grown thicker than the insulating layer.
6. The method of claim 2 , wherein the exposed portion of the floating gate layer is selectively etched without removing the exposed insulating layer.
7. The method of claim 4 , wherein forming the polysilicon film comprises chemical vapor deposition (CVD).