Method of manufacturing MOS transistor

1. A method of manufacturing a MOS transistor, comprising steps of:

implanting germanium ions to form a germanium implant layer in a surface of an active region defined by an isolation layer in a substrate;

implanting boron ions in the active region of the substrate to form a threshold voltage adjustment layer, the threshold voltage adjustment layer having a greater peak concentration depth than the germanium implant layer; and

thermally treating the substrate.

2. The method of claim 1 , wherein the germanium ion implanting step has an implant energy of about 5 to 50 keV and a concentration of 1×10 14 to 5×10 14 ions/cm 2 .

3. The method of claim 2 , wherein the boron ion implanting step has an implanting energy of about 10 to 50 keV and a concentration of 1×10 13 to 1×10 14 ions/cm 2 .

4. The method of claim 1 , wherein the thermal treating step comprises rapid thermal processing the substrate at a temperature of about 800 to 1000° C. in an N 2 ambient for 10 to 30 seconds.

5. The method of claim 1 , further comprising providing p-type semiconductor substrate.

6. The method of claim 1 , wherein the germanium ion implanting step has a concentration of 1×10 14 to 5×10 14 ions/cm 2 .

7. The method of claim 1 , wherein the boron ion implanting step has a concentration of 1×10 13 to 1×10 14 ions/cm 2 .

8. The method of claim 1 , wherein the germanium ion implanting step has an implanting energy of about 5 to 50 keV.

9. The method of claim 1 , wherein the boron ion implanting step has an implanting energy of about 10 to 50 keV.

10. A method of manufacturing a MOS transistor, comprising steps of:

implanting nitrogen ions in a semiconductor substrate having an active region defined by an isolation layer and a gate insulating layer and a gate thereon to form a nitrogen implant layer in the surface of the substrate on both sides of the gate;

implanting boron ions in the substrate to form lightly doped drain regions on both sides of the gate:

forming halo regions in a lower portion of the lightly doped drain regions by implanting third ions;

forming spacers on sidewalls of the gate;

implanting forth ions in the substrate on both sides of the spacers to form source/drain regions; and

thermally treating the substrate.

11. The method of claim 10 , wherein the nitrogen ion implanting step has an implanting energy of about 10 to 50 keV and a concentration of 1×10 14 to 5×10 14 ions/cm 2 .

12. The method of claim 11 , wherein the boron ion implanting step has an implanting energy of about 5 to 50 keV and a concentration of 1×10 14 to 5×10 15 ions/cm 2 .

13. The method of claim 10 , wherein the thermal treating step comprises rapid thermal processing the substrate at a temperature of about 600 to 800° C. in an N 2 ambient for 10 to 60 seconds.

14. The method of claim 10 , further comprising providing a n-type semiconductor substrate.

15. The method of claim 10 , wherein the third ions comprise As ions.

16. The method of claim 10 , wherein the fourth ions comprise B or BF 2 ions.

17. The method of claim 10 , further comprising implanting the third ions with an implanting energy of about 10 to 60 keV and a concentration of 1×10 14 to 1×10 15 ions/cm 2 .

18. The method of claim 10 , further comprising implanting the third ions at a tilt angle of 10° to 40°.

19. The method of claim 10 , further comprising implanting the fourth ions with an implanting energy of about 3 to 20 keV and a concentration of 1×10 15 to 5×10 15 ions/cm 2 .

20. The method of claim 10 , further comprising forming metal silicide layers on the gate and the source/drain regions.