Method for fabricating semiconductor device
View Patent ↗Method for fabricating a semiconductor device, including the steps of providing a first conductive type semiconductor substrate having a cell region and a logic region defined thereon, forming a first insulating film, second conductive type polysilicon, and a second insulating film in succession on the semiconductor substrate, selectively removing the first insulating film, the polysilicon, and the second insulating film, to form a floating gate pattern at the cell region, elevating a temperature initially in a state O 2 gas is injected, maintaining a fix temperature, and dropping the temperature in a state N 2 gas is injected, to form a gate oxide film on a surface of the semiconductor substrate at the logic region, and forming a gate electrode pattern at each of the cell region and the logic region, whereby preventing a threshold voltage of a semiconductor device from dropping due to infiltration of impurities from doped polysilicon at the cell region to the active channel region.
1. A method for fabricating a semiconductor device, comprising the steps of:
providing a first conductive type semiconductor substrate having a cell region and a logic region defined thereon;
forming a first insulating film, second conductive type polysilicon, and a second insulating film in succession on the semiconductor substrate;
selectively removing the first insulating film, the polysilicon, and the second insulating film, to form a floating gate pattern at the cell region;
elevating a temperature initially in a state O 2 gas is injected, maintaining a fix temperature, and dropping the temperature in a state N 2 gas is injected, to form a gate oxide film on a surface of the semiconductor substrate at the logic region; and
forming a gate electrode pattern at each of the cell region and the logic region.
2. The method as claimed in claim 1 , wherein the first insulating film is an ONO layer having an oxide film having a thickness of 15˜25 Å, a nitride film having a thickness of 90˜110 Å, and an oxide film having a thickness of 30˜50 Å.
3. The method as claimed in claim 1 , wherein the polysilicon is doped with second conductive type impurities and formed to a thickness in a range of 2000˜3000 Å.
4. The method as claimed in claim 1 , wherein the second insulating film is a bi-layered film having TEOS (Tetra-ethoxysilane) deposited to a thickness of 100˜200 Å, and a nitride film deposited to a thickness of 1200˜1800 Å.
5. The method as claimed in claim 1 , wherein the gate oxide film is formed to a thickness of 100˜150 Å.