IP Library Granted Patent US 7,232,746
Granted Patent B2
US 7,232,746 · App. 11/024,661 · Granted Jun 19, 2007

Method for forming dual damascene interconnection in semiconductor device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,232,746
App. No.
11/024,661
Granted
Jun 19, 2007
Kind
B2
Abstract

A method for forming a dual damascene interconnection in a semiconductor device, which is capable of preventing a lower metal film from being corroded. The method includes the steps of forming an etch stop film and an intermetal insulating film sequentially on a lower metal film to be interconnected, forming a via hole for exposing a portion of a surface of the etch stop film through the intermetal insulating film, and forming a trench having a width wider than that of the via hole on the intermetal insulating film. The method also includes the steps of exposing the lower metal film by removing the etch stop film by performing an etching process using an etching equipment of a dual plasma source, performing a nitrogen passivation process for the exposed lower metal film, and forming a barrier metal film and an upper metal film sequentially within the trench and the via hole.

Claims (24)

1. A method for forming a dual damascene interconnection in a semiconductor device, comprising the steps of:

forming an etch stop film and an intermetal insulating film sequentially on a lower metal film to be interconnected;

forming a via hole for exposing a portion of a surface of the etch stop film through the intermetal insulating film;

forming a trench having a width wider than a width of the via hole on the intermetal insulating film;

exposing the lower metal film by removing the etch stop film by performing an etching process using an etching equipment of a dual plasma source;

performing a nitrogen passivation process for the exposed lower metal film while a bias power of the etching equipment of the dual plasma source remains; and

forming a barrier metal film and an upper metal film sequentially within the trench and the via hole.

2. The method of claim 1 , wherein the etching process for removing the etch stop film is performed in an etching equipment of a dual plasma source under conditions of a source power of about 100 W to about 300 W, a bias power of about 500 W to about 1000 W, a pressure of about 20 mTorr to about 100 mTorr, and a volume of about 20 liters to about 45 liters.

3. The method of claim 2 , wherein the etching process for removing the etch stop film is performed using a CF 4 gas of about 10 sccm to about 50 sccm and an Ar gas of about 100 sccm to about 400 sccm.

4. The method of claim 1 , wherein the step of performing a nitrogen passivation process is performed in-situ with the etching process for removing the etch stop film using the etching equipment of the dual plasma source.

5. The method of claim 4 , wherein the step of performing a nitrogen passivation process is performed using a nitrogen gas of about 200 sccm to about 400 sccm for about 40 seconds to about one minute while a bias power of the etching equipment of the dual plasma source remains at about 500 W to about 1000 W and a pressure remains at about 100 mTorr to about 200 mTorr.

6. The method of claim 1 , wherein the lower metal film is made with a copper film, and the etch stop film is made with a nitride film.

7. A method for forming a dual damascene interconnection in a semiconductor device, comprising:

a step for forming an etch stop film and an intermetal insulating film sequentially on a lower metal film to be interconnected;

a step for forming a via hole for exposing a portion of a surface of the etch stop film through the intermetal insulating film;

a step for forming a trench having a width wider than a width of the via hole on the intermetal insulating film;

a step for exposing the lower metal film by removing the etch stop film by performing an etching process using an etching equipment of a dual plasma source;

a step for performing a nitrogen passivation process for the exposed lower metal film while a bias power of the etching equipment of the dual plasma source remains; and

a step for forming a barrier metal film and an upper metal film sequentially within the trench and the via hole.

8. The method of claim 7 , wherein the etching process for removing the etch stop film is performed in an etching equipment of a dual plasma source under conditions of a source power of about 100 W to about 300 W, a bias power of about 500 W to about 1000 W, a pressure of about 20 mTorr to about 100 mTorr, and a volume of about 20 liters to about 45 liters.

9. The method of claim 7 , wherein the etching process for removing the etch stop film is performed using a CF 4 gas of about 10 sccm to about 50 sccm and an Ar gas of about 100 sccm to about 400 sccm.

10. The method of claim 7 , wherein the step for performing a nitrogen passivation process is performed in-situ with the etching process for removing the etch stop film using the etching equipment of the dual plasma source.

11. The method of claim 10 , wherein the step for performing a nitrogen passivation process is performed using a nitrogen gas of about 200 sccm to about 400 sccm for about 40 seconds to about one minute while a bias power of the etching equipment of the dual plasma source remains at about 500 W to about 1000 W and a pressure remains at about 100 mTorr to about 200 mTorr.

12. The method of claim 7 , wherein the lower metal film is made with a copper film, and the etch stop film is made with a nitride film.

Assignments (8)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 27, 2021
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE LTD.
Reel/Frame 057336/0873 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: MARVELL TECHNOLOGY CAYMAN I
To: CAVIUM INTERNATIONAL
Reel/Frame 057279/0519 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 23, 2021
From: INPHI CORPORATION
To: MARVELL TECHNOLOGY CAYMAN I
Reel/Frame 056649/0823 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2017
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 041375/0886 →
CORRECTIVE ASSIGNMENT TO CORRECT REMOVE PATENT NO. 878209 FROM EXHIBIT B PREVIOUSLY RECORDED AT REEL: 034009 FRAME: 0157. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Oct 24, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034087/0097 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 15, 2014
From: DONGBU HITEK, CO., LTD.
To: INPHI CORPORATION
Reel/Frame 034009/0157 →
CHANGE OF NAME Recorded May 23, 2006
From: DONGBU-ANAM SEMICONDUCTOR, INC.
To: DONGBU ELECTRONICS CO., LTD.
Reel/Frame 017663/0468 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 30, 2004
From: SHIM, JOON-BUM
To: DONGBUANAM SEMICONDUCTOR INC.
Reel/Frame 016154/0597 →